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/linux-6.12.1/tools/arch/x86/kcpuid/
Dcpuid.csv2 # Generator: x86-cpuid-db v1.0
12 # Leaf 0H
15 … 0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported
16 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
17 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
18 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
23 1, 0, eax, 3:0, stepping , Stepping ID
24 1, 0, eax, 7:4, base_model , Base CPU model ID
25 1, 0, eax, 11:8, base_family_id , Base CPU family ID
26 1, 0, eax, 13:12, cpu_type , CPU type
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/include/x86_64/
Dprocessor.h35 #define NMI_VECTOR 0x02
39 #define X86_CR4_VME (1ul << 0)
70 u8 extended_state_area[0];
73 #define XFEATURE_MASK_FP BIT_ULL(0)
123 kvm_static_assert((fn & 0xc0000000) == 0 || \
124 (fn & 0xc0000000) == 0x40000000 || \
125 (fn & 0xc0000000) == 0x80000000 || \
126 (fn & 0xc0000000) == 0xc0000000); \
134 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3)
135 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5)
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-mc.yaml47 "^emc-timings-[0-9]+$":
56 "^timing-[0-9]+$":
118 reg = <0x70019000 0x1000>;
122 interrupts = <0 77 4>;
135 0x40040001 /* MC_EMEM_ARB_CFG */
136 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
137 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
138 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
139 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
140 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
[all …]
/linux-6.12.1/fs/smb/common/
Dsmbfsctl.h35 #define FSCTL_DEVICE_DFS (0x0006 << 16)
36 #define FSCTL_DEVICE_FILE_SYSTEM (0x0009 << 16)
37 #define FSCTL_DEVICE_NAMED_PIPE (0x0011 << 16)
38 #define FSCTL_DEVICE_NETWORK_FILE_SYSTEM (0x0014 << 16)
39 #define FSCTL_DEVICE_MASK 0xffff0000
41 #define FSCTL_DEVICE_ACCESS_FILE_ANY_ACCESS (0x00 << 14)
42 #define FSCTL_DEVICE_ACCESS_FILE_READ_ACCESS (0x01 << 14)
43 #define FSCTL_DEVICE_ACCESS_FILE_WRITE_ACCESS (0x02 << 14)
44 #define FSCTL_DEVICE_ACCESS_FILE_READ_WRITE_ACCESS (0x03 << 14)
45 #define FSCTL_DEVICE_ACCESS_MASK 0x0000c000
[all …]
Dsmb2status.h13 * 0 1 2 3 4 5 6 7 8 9 0 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
19 #define STATUS_SEVERITY_SUCCESS __constant_cpu_to_le32(0x0000)
20 #define STATUS_SEVERITY_INFORMATIONAL cpu_to_le32(0x0001)
21 #define STATUS_SEVERITY_WARNING cpu_to_le32(0x0002)
22 #define STATUS_SEVERITY_ERROR cpu_to_le32(0x0003)
30 #define STATUS_SUCCESS cpu_to_le32(0x00000000)
31 #define STATUS_WAIT_0 cpu_to_le32(0x00000000)
32 #define STATUS_WAIT_1 cpu_to_le32(0x00000001)
33 #define STATUS_WAIT_2 cpu_to_le32(0x00000002)
34 #define STATUS_WAIT_3 cpu_to_le32(0x00000003)
[all …]
/linux-6.12.1/arch/x86/kvm/
Dreverse_cpuid.h40 /* Intel-defined SGX sub-features, CPUID level 0x12 (EAX). */
41 #define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0)
45 /* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
52 /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */
53 #define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0)
60 /* Intel-defined sub-features, CPUID level 0x00000024:0 (EBX) */
65 /* CPUID level 0x80000007 (EDX). */
68 /* CPUID level 0x80000022 (EAX) */
69 #define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0)
78 [CPUID_1_EDX] = { 1, 0, CPUID_EDX},
[all …]
Dcpuid.c41 int feature_bit = 0; in xstate_required_size()
46 if (xstate_bv & 0x1) { in xstate_required_size()
48 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); in xstate_required_size()
51 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; in xstate_required_size()
70 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \
100 for (i = 0; i < nent; i++) { in cpuid_entry2_find()
144 best = cpuid_entry2_find(entries, nent, 0x80000008, in kvm_check_cpuid()
147 int vaddr_bits = (best->eax & 0xff00) >> 8; in kvm_check_cpuid()
149 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) in kvm_check_cpuid()
157 best = cpuid_entry2_find(entries, nent, 0xd, 0); in kvm_check_cpuid()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/include/nvif/
Dclass.h6 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
8 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
10 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
11 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
12 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
13 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
15 #define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
16 #define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
17 #define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
18 #define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
[all …]
/linux-6.12.1/arch/x86/include/asm/
Dsvm.h16 INTERCEPT_CR = 0,
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
155 u64 avic_backing_page; /* Offset 0xe0 */
156 u8 reserved_6[8]; /* Offset 0xe8 */
157 u64 avic_logical_id; /* Offset 0xf0 */
158 u64 avic_physical_id; /* Offset 0xf8 */
163 * Offset 0x3e0, 32 bytes reserved
173 #define TLB_CONTROL_DO_NOTHING 0
178 #define V_TPR_MASK 0x0f
[all …]
Dcpufeatures.h28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* "fpu" Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* "vme" Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* "de" Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* "pae" Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* "mce" Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/linux-6.12.1/arch/x86/kernel/cpu/
Dcommon.c210 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
211 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
212 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff),
213 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
214 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff),
215 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff),
217 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
218 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
219 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
220 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff),
[all …]
/linux-6.12.1/fs/ntfs3/
Dntfs.h30 * ntfs.sys used 500 maximum links on-disk struct allows up to 0xffff.
55 * at offset 0x40.
86 MFT_REC_MFT = 0,
104 ATTR_ZERO = cpu_to_le32(0x00),
105 ATTR_STD = cpu_to_le32(0x10),
106 ATTR_LIST = cpu_to_le32(0x20),
107 ATTR_NAME = cpu_to_le32(0x30),
108 ATTR_ID = cpu_to_le32(0x40),
109 ATTR_SECURE = cpu_to_le32(0x50),
110 ATTR_LABEL = cpu_to_le32(0x60),
[all …]
/linux-6.12.1/tools/arch/x86/include/asm/
Dcpufeatures.h28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* "fpu" Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* "vme" Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* "de" Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* "pae" Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* "mce" Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */
[all …]
/linux-6.12.1/arch/x86/kvm/svm/
Dsvm.c133 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18,
135 * intercept the MSR 0x832, and do not setup direct_access_msr.
260 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
271 for (i = 0; i < NUM_MSR_MAPS; i++) { in svm_msrpm_offset()
347 return 0; in svm_set_efer()
353 u32 ret = 0; in svm_get_interrupt_shadow()
364 if (mask == 0) in svm_set_interrupt_shadow()
384 if (nrips && svm->vmcb->control.next_rip != 0) { in __svm_skip_emulated_instruction()
394 return 0; in __svm_skip_emulated_instruction()
404 svm_set_interrupt_shadow(vcpu, 0); in __svm_skip_emulated_instruction()
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtw88/
Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]