Lines Matching +full:0 +full:x8000000a
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
29 #define X86_FEATURE_FPU ( 0*32+ 0) /* "fpu" Onboard FPU */
30 #define X86_FEATURE_VME ( 0*32+ 1) /* "vme" Virtual Mode Extensions */
31 #define X86_FEATURE_DE ( 0*32+ 2) /* "de" Debugging Extensions */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */
33 #define X86_FEATURE_TSC ( 0*32+ 4) /* "tsc" Time Stamp Counter */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
35 #define X86_FEATURE_PAE ( 0*32+ 6) /* "pae" Physical Address Extensions */
36 #define X86_FEATURE_MCE ( 0*32+ 7) /* "mce" Machine Check Exception */
37 #define X86_FEATURE_CX8 ( 0*32+ 8) /* "cx8" CMPXCHG8 instruction */
38 #define X86_FEATURE_APIC ( 0*32+ 9) /* "apic" Onboard APIC */
39 #define X86_FEATURE_SEP ( 0*32+11) /* "sep" SYSENTER/SYSEXIT */
40 #define X86_FEATURE_MTRR ( 0*32+12) /* "mtrr" Memory Type Range Registers */
41 #define X86_FEATURE_PGE ( 0*32+13) /* "pge" Page Global Enable */
42 #define X86_FEATURE_MCA ( 0*32+14) /* "mca" Machine Check Architecture */
43 #define X86_FEATURE_CMOV ( 0*32+15) /* "cmov" CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
44 #define X86_FEATURE_PAT ( 0*32+16) /* "pat" Page Attribute Table */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
46 #define X86_FEATURE_PN ( 0*32+18) /* "pn" Processor serial number */
47 #define X86_FEATURE_CLFLUSH ( 0*32+19) /* "clflush" CLFLUSH instruction */
48 #define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
49 #define X86_FEATURE_ACPI ( 0*32+22) /* "acpi" ACPI via MSR */
50 #define X86_FEATURE_MMX ( 0*32+23) /* "mmx" Multimedia Extensions */
51 #define X86_FEATURE_FXSR ( 0*32+24) /* "fxsr" FXSAVE/FXRSTOR, CR4.OSFXSR */
52 #define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
53 #define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
54 #define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
55 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
56 #define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
58 #define X86_FEATURE_PBE ( 0*32+31) /* "pbe" Pending Break Enable */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
74 #define X86_FEATURE_RECOVERY ( 2*32+ 0) /* "recovery" CPU in recovery mode */
80 #define X86_FEATURE_CXMMX ( 3*32+ 0) /* "cxmmx" Cyrix MMX extensions */
100 #define X86_FEATURE_NOPL ( 3*32+20) /* "nopl" The NOPL (0F 1F) instructions */
113 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
114 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
146 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
158 /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
159 #define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* "lahf_lm" LAHF/SAHF in long mode */
188 * CPUID levels like 0x6, 0xA etc, word 7.
192 #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* "ring3mwait" Ring 3 MONITOR/MWAIT instructions */
226 #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* "tpr_shadow" Intel TPR Shadow */
240 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
241 #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* "fsgsbase" RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instr…
242 #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* "tsc_adjust" TSC adjustment MSR 0x3B */
273 /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */
274 #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* "xsaveopt" XSAVEOPT instruction */
282 * CPUID levels like 0xf, etc.
286 #define X86_FEATURE_CQM_LLC (11*32+ 0) /* "cqm_llc" LLC QoS if 1 */
319 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
334 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
335 #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */
354 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
355 #define X86_FEATURE_DTHERM (14*32+ 0) /* "dtherm" Digital Thermal Sensor */
368 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
369 #define X86_FEATURE_NPT (15*32+ 0) /* "npt" Nested Page Table support */
387 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
411 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
412 #define X86_FEATURE_OVERFLOW_RECOV (17*32+ 0) /* "overflow_recov" MCA overflow recovery support */
416 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
442 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
443 #define X86_FEATURE_SME (19*32+ 0) /* "sme" AMD Secure Memory Encryption */
453 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
454 #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */
467 * CPUID levels like 0x80000022, etc and Linux defined features.
471 #define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* "amd_lbr_pmc_freeze" AMD LBR and PMC Freeze */
483 #define X86_BUG_F00F X86_BUG(0) /* "f00f" Intel F00F */
523 #define X86_BUG_SRSO X86_BUG(1*32 + 0) /* "srso" AMD SRSO bug */