Home
last modified time | relevance | path

Searched +full:0 +full:x4d0 (Results 1 – 25 of 71) sorted by relevance

123

/linux-6.12.1/drivers/staging/olpc_dcon/
Dolpc_dcon_xo_1.c43 const struct dcon_gpio *pin = &gpios_asis[0]; in dcon_init_xo_1()
45 for (i = 0; i < ARRAY_SIZE(gpios_asis); i++) { in dcon_init_xo_1()
85 cs5535_gpio_setup_event(OLPC_GPIO_DCON_IRQ, 2, 0); in dcon_init_xo_1()
91 lob = inb(0x4d0); in dcon_init_xo_1()
93 outb(lob, 0x4d0); in dcon_init_xo_1()
96 if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", dcon)) { in dcon_init_xo_1()
124 cs5535_gpio_set(0, GPIO_FLTR7_AMOUNT); in dcon_init_xo_1()
138 return 0; in dcon_init_xo_1()
167 for (x = 0; x < 16; x++) { in dcon_wiggle_xo_1()
193 return 0; in dcon_read_status_xo_1()
/linux-6.12.1/arch/x86/include/asm/
Di8259.h11 #define cached_master_mask (__byte(0, cached_irq_mask))
15 #define PIC_MASTER_CMD 0x20
16 #define PIC_MASTER_IMR 0x21
20 #define PIC_SLAVE_CMD 0xa0
21 #define PIC_SLAVE_IMR 0xa1
22 #define PIC_ELCR1 0x4d0
23 #define PIC_ELCR2 0x4d1
27 #define MASTER_ICW4_DEFAULT 0x01
28 #define SLAVE_ICW4_DEFAULT 0x01
/linux-6.12.1/include/linux/
Deisa.h16 #define EISA_INT1_CTRL 0x20
17 #define EISA_INT1_MASK 0x21
18 #define EISA_INT2_CTRL 0xA0
19 #define EISA_INT2_MASK 0xA1
20 #define EISA_DMA2_STATUS 0xD0
21 #define EISA_DMA2_WRITE_SINGLE 0xD4
22 #define EISA_EXT_NMI_RESET_CTRL 0x461
23 #define EISA_INT1_EDGE_LEVEL 0x4D0
24 #define EISA_INT2_EDGE_LEVEL 0x4D1
25 #define EISA_VENDOR_ID_OFFSET 0xC80
[all …]
Dcs5535.h14 #define MSR_GLIU_P2D_RO0 0x10000029
16 #define MSR_LX_GLD_MSR_CONFIG 0x48002001
17 #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
19 #define MSR_GLCP_SYS_RSTPLL 0x4C000014
20 #define MSR_GLCP_DOTPLL 0x4C000015
22 #define MSR_LBAR_SMB 0x5140000B
23 #define MSR_LBAR_GPIO 0x5140000C
24 #define MSR_LBAR_MFGPT 0x5140000D
25 #define MSR_LBAR_ACPI 0x5140000E
26 #define MSR_LBAR_PMS 0x5140000F
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/linux-6.12.1/arch/x86/kvm/
Di8259.c75 if (s != &s->pics_state->pics[0]) in pic_clear_isr()
106 if ((s->last_irr & mask) == 0) { in pic_set_irq1()
124 if (mask == 0) in get_priority()
126 priority = 0; in get_priority()
127 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) in get_priority()
149 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) in pic_get_irq()
170 if (irq2 >= 0) { in pic_update_irq()
174 pic_set_irq1(&s->pics[0], 2, 1); in pic_update_irq()
175 pic_set_irq1(&s->pics[0], 2, 0); in pic_update_irq()
177 irq = pic_get_irq(&s->pics[0]); in pic_update_irq()
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dxlnx,nwl-pcie.yaml50 - const: 0
51 - const: 0
52 - const: 0
87 const: 0
125 reg = <0x0 0xfd0e0000 0x0 0x1000>,
126 <0x0 0xfd480000 0x0 0x1000>,
127 <0x80 0x00000000 0x0 0x10000000>;
129 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
130 <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
141 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
[all …]
/linux-6.12.1/drivers/staging/rtl8723bs/hal/
Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Dphy_lcn.c66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup()
67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup()
70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup()
71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup()
72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup()
73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup()
74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup()
75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup()
76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup()
77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup()
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]
/linux-6.12.1/drivers/soc/imx/
Dsoc-imx.c16 #define IIM_UID 0x820
18 #define OCOTP_UID_H 0x420
19 #define OCOTP_UID_L 0x410
21 #define OCOTP_ULP_UID_1 0x4b0
22 #define OCOTP_ULP_UID_2 0x4c0
23 #define OCOTP_ULP_UID_3 0x4d0
24 #define OCOTP_ULP_UID_4 0x4e0
34 u64 soc_uid = 0; in imx_soc_device_init()
41 return 0; in imx_soc_device_init()
155 soc_uid = val & 0xffff; in imx_soc_device_init()
[all …]
/linux-6.12.1/drivers/parisc/
Deisa.c45 #if 0
51 #define SNAKES_EEPROM_BASE_ADDR 0xF0810400
52 #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
71 if (port & 0x300) { in eisa_permute()
72 return 0xfc000000 | ((port & 0xfc00) >> 6) in eisa_permute()
73 | ((port & 0x3f8) << 9) | (port & 7); in eisa_permute()
75 return 0xfc000000 | port; in eisa_permute()
83 return 0xff; in eisa_in8()
90 return 0xffff; in eisa_in16()
97 return 0xffffffff; in eisa_in32()
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dmpc8544ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x800000>;
44 partition@0 {
45 reg = <0x0 0x10000>;
50 reg = <0x20000 0x30000>;
56 reg = <0x200000 0x200000>;
62 reg = <0x400000 0x380000>;
67 reg = <0x780000 0x80000>;
82 phy0: ethernet-phy@0 {
83 interrupts = <10 1 0 0>;
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/asp2/
Dbcmasp_intf_defs.h6 ((((intf)->port) * 0x800) + 0xc000)
7 #define UMC_CMD 0x008
8 #define UMC_CMD_TX_EN BIT(0)
10 #define UMC_CMD_SPEED_SHIFT 0x2
11 #define UMC_CMD_SPEED_MASK 0x3
12 #define UMC_CMD_SPEED_10 0x0
13 #define UMC_CMD_SPEED_100 0x1
14 #define UMC_CMD_SPEED_1000 0x2
15 #define UMC_CMD_SPEED_2500 0x3
33 #define UMC_MAC0 0x0c
[all …]
/linux-6.12.1/arch/arm/mach-orion5x/
Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_engine_regs.h18 #define RENDER_RING_BASE 0x02000
19 #define BSD_RING_BASE 0x1c0000
20 #define BSD2_RING_BASE 0x1c4000
21 #define BSD3_RING_BASE 0x1d0000
22 #define BSD4_RING_BASE 0x1d4000
23 #define XEHP_BSD5_RING_BASE 0x1e0000
24 #define XEHP_BSD6_RING_BASE 0x1e4000
25 #define XEHP_BSD7_RING_BASE 0x1f0000
26 #define XEHP_BSD8_RING_BASE 0x1f4000
27 #define VEBOX_RING_BASE 0x1c8000
[all …]
/linux-6.12.1/drivers/net/ethernet/apple/
Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/linux-6.12.1/arch/powerpc/sysdev/
Di8259.c17 static unsigned char cached_8259[2] = { 0xff, 0xff };
18 #define cached_A1 (cached_8259[0])
34 int lock = 0; in i8259_irq()
44 outb(0x0C, 0x20); /* prepare for poll */ in i8259_irq()
45 irq = inb(0x20) & 7; in i8259_irq()
51 outb(0x0C, 0xA0); /* prepare for poll */ in i8259_irq()
52 irq = (inb(0xA0) & 7) + 8; in i8259_irq()
65 outb(0x0B, 0x20); /* ISR register */ in i8259_irq()
66 if(~inb(0x20) & 0x80) in i8259_irq()
67 irq = 0; in i8259_irq()
[all …]

123