Lines Matching +full:0 +full:x4d0

14 #define MSR_GLIU_P2D_RO0	0x10000029
16 #define MSR_LX_GLD_MSR_CONFIG	0x48002001
17 #define MSR_LX_MSR_PADSEL	0x48002011	/* NOT 0x48000011; the data
19 #define MSR_GLCP_SYS_RSTPLL	0x4C000014
20 #define MSR_GLCP_DOTPLL		0x4C000015
22 #define MSR_LBAR_SMB		0x5140000B
23 #define MSR_LBAR_GPIO		0x5140000C
24 #define MSR_LBAR_MFGPT		0x5140000D
25 #define MSR_LBAR_ACPI		0x5140000E
26 #define MSR_LBAR_PMS		0x5140000F
28 #define MSR_DIVIL_SOFT_RESET	0x51400017
30 #define MSR_PIC_YSEL_LOW	0x51400020
31 #define MSR_PIC_YSEL_HIGH	0x51400021
32 #define MSR_PIC_ZSEL_LOW	0x51400022
33 #define MSR_PIC_ZSEL_HIGH	0x51400023
34 #define MSR_PIC_IRQM_LPC	0x51400025
36 #define MSR_MFGPT_IRQ		0x51400028
37 #define MSR_MFGPT_NR		0x51400029
38 #define MSR_MFGPT_SETUP		0x5140002B
40 #define MSR_RTC_DOMA_OFFSET	0x51400055
41 #define MSR_RTC_MONA_OFFSET	0x51400056
42 #define MSR_RTC_CEN_OFFSET	0x51400057
44 #define MSR_LX_SPARE_MSR	0x80000011	/* DC-specific */
46 #define MSR_GX_GLD_MSR_CONFIG	0xC0002001
47 #define MSR_GX_MSR_PADSEL	0xC0002011
55 	lo &= ~(0xF << (group * 4));  in cs5535_pic_unreqz_select_high()
56 	lo |= (irq & 0xF) << (group * 4);  in cs5535_pic_unreqz_select_high()
58 	return 0;  in cs5535_pic_unreqz_select_high()
62 #define CS5536_PIC_INT_SEL1	0x4d0
63 #define CS5536_PIC_INT_SEL2	0x4d1
66 #define LBAR_GPIO_SIZE		0xFF
67 #define LBAR_MFGPT_SIZE		0x40
68 #define LBAR_ACPI_SIZE		0x40
69 #define LBAR_PMS_SIZE		0x80
76 #define CS5536_PM_SCLK		0x10
77 #define CS5536_PM_IN_SLPCTL	0x20
78 #define CS5536_PM_WKXD		0x34
79 #define CS5536_PM_WKD		0x30
80 #define CS5536_PM_SSC		0x54
87 #define CS5536_PM1_STS		0x00
88 #define CS5536_PM1_EN		0x02
89 #define CS5536_PM1_CNT		0x08
90 #define CS5536_PM_GPE0_STS	0x18
91 #define CS5536_PM_GPE0_EN	0x1c
111 #define VSA_VRC_INDEX		0xAC1C
112 #define VSA_VRC_DATA		0xAC1E
113 #define VSA_VR_UNLOCK		0xFC53  /* unlock virtual register */
114 #define VSA_VR_SIGNATURE	0x0003
115 #define VSA_VR_MEM_SIZE		0x0200
116 #define AMD_VSA_SIG		0x4132  /* signature is ascii 'VSA2' */
117 #define GSW_VSA_SIG		0x534d  /* General Software signature */
143 #define GPIO_OUTPUT_VAL		0x00
144 #define GPIO_OUTPUT_ENABLE	0x04
145 #define GPIO_OUTPUT_OPEN_DRAIN	0x08
146 #define GPIO_OUTPUT_INVERT	0x0C
147 #define GPIO_OUTPUT_AUX1	0x10
148 #define GPIO_OUTPUT_AUX2	0x14
149 #define GPIO_PULL_UP		0x18
150 #define GPIO_PULL_DOWN		0x1C
151 #define GPIO_INPUT_ENABLE	0x20
152 #define GPIO_INPUT_INVERT	0x24
153 #define GPIO_INPUT_FILTER	0x28
154 #define GPIO_INPUT_EVENT_COUNT	0x2C
155 #define GPIO_READ_BACK		0x30
156 #define GPIO_INPUT_AUX1		0x34
157 #define GPIO_EVENTS_ENABLE	0x38
158 #define GPIO_LOCK_ENABLE	0x3C
159 #define GPIO_POSITIVE_EDGE_EN	0x40
160 #define GPIO_NEGATIVE_EDGE_EN	0x44
161 #define GPIO_POSITIVE_EDGE_STS	0x48
162 #define GPIO_NEGATIVE_EDGE_STS	0x4C
164 #define GPIO_FLTR7_AMOUNT	0xD8
166 #define GPIO_MAP_X		0xE0
167 #define GPIO_MAP_Y		0xE4
168 #define GPIO_MAP_Z		0xE8
169 #define GPIO_MAP_W		0xEC
171 #define GPIO_FE7_SEL		0xF7
188 #define MFGPT_CMP1		0
191 #define MFGPT_EVENT_IRQ		0
195 #define MFGPT_REG_CMP1		0
233 	return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);  in cs5535_mfgpt_release_irq()