/linux-6.12.1/Documentation/devicetree/bindings/pci/ |
D | ti,am65-pci-ep.yaml | 66 reg = <0x5500000 0x1000>, 67 <0x5501000 0x1000>, 68 <0x10000000 0x8000000>, 69 <0x5506000 0x1000>; 72 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
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D | ti,am65-pci-host.yaml | 70 pattern: '^pcie-phy[0-1]$' 104 reg = <0x5500000 0x1000>, 105 <0x5501000 0x1000>, 106 <0x10000000 0x2000>, 107 <0x5506000 0x1000>; 112 ranges = <0x81000000 0 0 0x10020000 0 0x00010000>, 113 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>; 114 ti,syscon-pcie-id = <&scm_conf 0x0210>; 115 ti,syscon-pcie-mode = <&scm_conf 0x4060>; 116 bus-range = <0x0 0xff>; [all …]
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/linux-6.12.1/drivers/net/ethernet/tehuti/ |
D | tn40_regs.h | 8 #define TN40_REGS_SIZE 0x10000 10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ 11 #define TN40_REG_TXD_CFG1_0 0x4000 12 #define TN40_REG_TXD_CFG1_1 0x4004 13 #define TN40_REG_TXD_CFG1_2 0x4008 14 #define TN40_REG_TXD_CFG1_3 0x400C 16 #define TN40_REG_RXF_CFG1_0 0x4010 17 #define TN40_REG_RXF_CFG1_1 0x4014 18 #define TN40_REG_RXF_CFG1_2 0x4018 19 #define TN40_REG_RXF_CFG1_3 0x401C [all …]
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D | tehuti.h | 81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff) 83 # define H32_64(x) 0 105 # define NETDEV_TX_OK 0 134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0) 189 * if len == 0 addr is dma 190 * if len != 0 addr is skb */ 207 u64 InUCast; /* 0x7200 */ 208 u64 InMCast; /* 0x7210 */ 209 u64 InBCast; /* 0x7220 */ 210 u64 InPkts; /* 0x7230 */ [all …]
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/linux-6.12.1/arch/m68k/fpsp040/ |
D | bugfix.S | 21 | dirty_bit[cmdreg3b[9:7]] = 0; 181 andib #0xFE,%d0 191 | Check for opclass 0. If not, go and check for opclass 2 and sgl. 194 andiw #0xE000,%d0 |strip all but opclass 195 bne op2sgl |not opclass 0, check op2 222 | We have the opclass 0 situation. 232 moveb #0x12,%d0 233 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended 269 andil #0xe0000000,L_SCR3(%a6) 270 moveb #0,CU_SAVEPC(%a6) [all …]
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/linux-6.12.1/include/ufs/ |
D | unipro.h | 12 #define TX_HIBERN8TIME_CAPABILITY 0x000F 13 #define TX_MODE 0x0021 14 #define TX_HSRATE_SERIES 0x0022 15 #define TX_HSGEAR 0x0023 16 #define TX_PWMGEAR 0x0024 17 #define TX_AMPLITUDE 0x0025 18 #define TX_HS_SLEWRATE 0x0026 19 #define TX_SYNC_SOURCE 0x0027 20 #define TX_HS_SYNC_LENGTH 0x0028 21 #define TX_HS_PREPARE_LENGTH 0x0029 [all …]
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/linux-6.12.1/drivers/scsi/ |
D | hptiop.h | 30 #define IOPMU_QUEUE_EMPTY 0xffffffff 31 #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000 32 #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000 33 #define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000 34 #define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000 40 #define IOPMU_OUTBOUND_INT_PCI 0x10 46 #define IOPMU_INBOUND_INT_POSTQUEUE 0x10 63 __le32 reserved[0x20400 / 4]; 72 __le32 reserved0[(0x4000 - 0) / 4]; 75 __le32 reserved1[(0x4018 - 0x4008) / 4]; [all …]
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/linux-6.12.1/include/video/ |
D | permedia2.h | 17 #define PM2_REGS_SIZE 0x10000 19 #define PM2TAG(r) (u32 )(((r)-0x8000)>>3) 25 #define PM2R_RESET_STATUS 0x0000 26 #define PM2R_IN_FIFO_SPACE 0x0018 27 #define PM2R_OUT_FIFO_WORDS 0x0020 28 #define PM2R_APERTURE_ONE 0x0050 29 #define PM2R_APERTURE_TWO 0x0058 30 #define PM2R_FIFO_DISCON 0x0068 31 #define PM2R_CHIP_CONFIG 0x0070 33 #define PM2R_REBOOT 0x1000 [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/mxs/ |
D | imx28-pinfunc.h | 13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000 14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010 15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020 16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030 17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040 18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050 19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060 20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070 21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100 22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110 [all …]
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/linux-6.12.1/include/linux/mfd/wm831x/ |
D | core.h | 25 #define WM831X_RESET_ID 0x00 26 #define WM831X_REVISION 0x01 27 #define WM831X_PARENT_ID 0x4000 28 #define WM831X_SYSVDD_CONTROL 0x4001 29 #define WM831X_THERMAL_MONITORING 0x4002 30 #define WM831X_POWER_STATE 0x4003 31 #define WM831X_WATCHDOG 0x4004 32 #define WM831X_ON_PIN_CONTROL 0x4005 33 #define WM831X_RESET_CONTROL 0x4006 34 #define WM831X_CONTROL_INTERFACE 0x4007 [all …]
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D | regulator.h | 14 * R16462 (0x404E) - Current Sink 1 16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */ 17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */ 20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */ 21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */ 24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */ 25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */ 28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */ 31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */ 34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */ [all …]
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/linux-6.12.1/net/mac80211/ |
D | tkip.c | 28 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, 29 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, 30 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B, 31 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B, 32 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F, 33 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F, 34 0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5, 35 0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F, 36 0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB, 37 0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397, [all …]
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/linux-6.12.1/arch/powerpc/include/asm/ |
D | spu.h | 23 #define MFC_PUT_CMD 0x20 24 #define MFC_PUTS_CMD 0x28 25 #define MFC_PUTR_CMD 0x30 26 #define MFC_PUTF_CMD 0x22 27 #define MFC_PUTB_CMD 0x21 28 #define MFC_PUTFS_CMD 0x2A 29 #define MFC_PUTBS_CMD 0x29 30 #define MFC_PUTRF_CMD 0x32 31 #define MFC_PUTRB_CMD 0x31 32 #define MFC_PUTL_CMD 0x24 [all …]
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/linux-6.12.1/drivers/net/wireless/ath/ath9k/ |
D | reg.h | 22 #define AR_CR 0x0008 23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004) 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 27 #define AR_RXDP 0x000C 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 [all …]
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/linux-6.12.1/drivers/scsi/qla2xxx/ |
D | qla_dbg.c | 13 * | Module Init and Probe | 0x0199 | | 14 * | Mailbox commands | 0x1206 | 0x11a5-0x11ff | 15 * | Device Discovery | 0x2134 | 0x2112-0x2115 | 16 * | | | 0x2127-0x2128 | 17 * | Queue Command and IO tracing | 0x3074 | 0x300b | 18 * | | | 0x3027-0x3028 | 19 * | | | 0x303d-0x3041 | 20 * | | | 0x302e,0x3033 | 21 * | | | 0x3036,0x3038 | 22 * | | | 0x303a | [all …]
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/linux-6.12.1/drivers/staging/rtl8192e/ |
D | rtllib_crypt_tkip.c | 69 priv->tx_tfm_michael = crypto_alloc_shash("michael_mic", 0, 0); in rtllib_tkip_init() 76 priv->rx_tfm_michael = crypto_alloc_shash("michael_mic", 0, 0); in rtllib_tkip_init() 112 return val & 0xff; in Lo8() 122 return val & 0xffff; in Lo16() 141 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, 142 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, 143 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B, 144 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B, 145 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F, 146 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F, [all …]
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/linux-6.12.1/drivers/gpu/drm/msm/adreno/ |
D | a4xx_gpu.c | 30 for (i = 0; i < submit->nr_cmds; i++) { in a4xx_submit() 61 OUT_RING(ring, 0x00000000); in a4xx_submit() 80 for (i = 0; i < 4; i++) in a4xx_enable_hwcg() 81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg() 82 for (i = 0; i < 4; i++) in a4xx_enable_hwcg() 83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg() 84 for (i = 0; i < 4; i++) in a4xx_enable_hwcg() 85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg() 86 for (i = 0; i < 4; i++) in a4xx_enable_hwcg() 87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg() [all …]
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/linux-6.12.1/net/wireless/ |
D | lib80211_crypt_tkip.c | 103 priv->tx_tfm_michael = crypto_alloc_shash("michael_mic", 0, 0); in lib80211_tkip_init() 109 priv->rx_tfm_michael = crypto_alloc_shash("michael_mic", 0, 0); in lib80211_tkip_init() 144 return val & 0xff; in Lo8() 154 return val & 0xffff; in Lo16() 173 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, 174 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, 175 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B, 176 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B, 177 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F, 178 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F, [all …]
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/linux-6.12.1/drivers/net/ethernet/renesas/ |
D | rswitch.h | 17 for (i = 0; i < RSWITCH_NUM_PORTS; i++) \ 23 for (; i-- > 0; ) \ 44 #define RSWITCH_TOP_OFFSET 0x00008000 45 #define RSWITCH_COMA_OFFSET 0x00009000 46 #define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ 47 #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ 48 #define RSWITCH_GWCA0_OFFSET 0x00010000 49 #define RSWITCH_GWCA1_OFFSET 0x00012000 55 #define GWCA_INDEX 0 57 #define GWCA_IPV_NUM 0 [all …]
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/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/pcie/ |
D | drv.c | 20 #define TRANS_CFG_MARKER BIT(0) 27 __builtin_choose_expr(_IS_A(cfg, iwl_cfg), 0, _invalid_type))) 38 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ 39 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ 40 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ 41 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ 42 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ 43 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ 44 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ 45 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ [all …]
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/linux-6.12.1/drivers/media/i2c/ |
D | ov08x40.c | 18 #define OV08X40_REG_MODE_SELECT 0x0100 19 #define OV08X40_MODE_STANDBY 0x00 20 #define OV08X40_MODE_STREAMING 0x01 22 #define OV08X40_REG_AO_STANDBY 0x1000 23 #define OV08X40_AO_STREAMING 0x04 25 #define OV08X40_REG_MS_SELECT 0x1001 26 #define OV08X40_MS_STANDBY 0x00 27 #define OV08X40_MS_STREAMING 0x04 29 #define OV08X40_REG_SOFTWARE_RST 0x0103 30 #define OV08X40_SOFTWARE_RST 0x01 [all …]
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/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/ |
D | rvu_reg.h | 12 #define RVU_AF_MSIXTR_BASE (0x10) 13 #define RVU_AF_ECO (0x20) 14 #define RVU_AF_BLK_RST (0x30) 15 #define RVU_AF_PF_BAR4_ADDR (0x40) 16 #define RVU_AF_RAS (0x100) 17 #define RVU_AF_RAS_W1S (0x108) 18 #define RVU_AF_RAS_ENA_W1S (0x110) 19 #define RVU_AF_RAS_ENA_W1C (0x118) 20 #define RVU_AF_GEN_INT (0x120) 21 #define RVU_AF_GEN_INT_W1S (0x128) [all …]
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/linux-6.12.1/drivers/net/ethernet/agere/ |
D | et131x.h | 53 #define LBCIF_DWORD0_GROUP 0xAC 54 #define LBCIF_DWORD1_GROUP 0xB0 57 #define LBCIF_ADDRESS_REGISTER 0xAC 58 #define LBCIF_DATA_REGISTER 0xB0 59 #define LBCIF_CONTROL_REGISTER 0xB1 60 #define LBCIF_STATUS_REGISTER 0xB2 63 #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01 64 #define LBCIF_CONTROL_PAGE_WRITE 0x02 65 #define LBCIF_CONTROL_EEPROM_RELOAD 0x08 66 #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20 [all …]
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/linux-6.12.1/drivers/net/ethernet/marvell/mvpp2/ |
D | mvpp2.h | 28 #define MVPP2_XDP_PASS 0 29 #define MVPP2_XDP_DROPPED BIT(0) 34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 37 #define MVPP2_RX_FIFO_INIT_REG 0x64 38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) [all …]
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/linux-6.12.1/arch/arm64/boot/dts/ti/ |
D | k3-am65-main.dtsi | 12 reg = <0x0 0x70000000 0x0 0x200000>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 22 reg = <0xf0000 0x10000>; 26 reg = <0x100000 0x100000>; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ [all …]
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