Lines Matching +full:0 +full:x4060
30 #define IOPMU_QUEUE_EMPTY 0xffffffff
31 #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000
32 #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000
33 #define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000
34 #define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000
40 #define IOPMU_OUTBOUND_INT_PCI 0x10
46 #define IOPMU_INBOUND_INT_POSTQUEUE 0x10
63 __le32 reserved[0x20400 / 4];
72 __le32 reserved0[(0x4000 - 0) / 4];
75 __le32 reserved1[(0x4018 - 0x4008) / 4];
77 __le32 reserved2[(0x402c - 0x401c) / 4];
79 __le32 reserved3[(0x4050 - 0x4030) / 4];
84 __le32 reserved4[(0x4088 - 0x4060) / 4];
87 __le32 reserved5[(0x1020c - 0x4090) / 4];
89 __le32 reserved6[(0x10400 - 0x10210) / 4];
91 __le32 reserved7[(0x10420 - 0x10404) / 4];
93 __le32 reserved8[(0x10480 - 0x10424) / 4];
109 #define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full))
112 #define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32 0xffffffff
121 #define CL_POINTER_TOGGLE 0x00004000
122 #define CPU_TO_F0_DRBL_MSG_BIT 0x02000000
126 IOPMU_INBOUND_MSG0_NOP = 0,
133 IOPMU_INBOUND_MSG0_MAX = 0xff,
135 IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
136 IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
137 IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
138 IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
139 IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
140 IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
156 #define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */
159 IOP_REQUEST_TYPE_GET_CONFIG = 0,
168 IOP_RESULT_PENDING = 0,
365 #define HPT_IOCTL_RESULT_OK 0
368 #if 0
369 #define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0)