Lines Matching +full:0 +full:x4060
81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
83 # define H32_64(x) 0
105 # define NETDEV_TX_OK 0
134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
189 * if len == 0 addr is dma
190 * if len != 0 addr is skb */
207 u64 InUCast; /* 0x7200 */
208 u64 InMCast; /* 0x7210 */
209 u64 InBCast; /* 0x7220 */
210 u64 InPkts; /* 0x7230 */
211 u64 InErrors; /* 0x7240 */
212 u64 InDropped; /* 0x7250 */
213 u64 FrameTooLong; /* 0x7260 */
214 u64 FrameSequenceErrors; /* 0x7270 */
215 u64 InVLAN; /* 0x7280 */
216 u64 InDroppedDFE; /* 0x7290 */
217 u64 InDroppedIntFull; /* 0x72A0 */
218 u64 InFrameAlignErrors; /* 0x72B0 */
220 /* 0x72C0-0x72E0 RSRV */
222 u64 OutUCast; /* 0x72F0 */
223 u64 OutMCast; /* 0x7300 */
224 u64 OutBCast; /* 0x7310 */
225 u64 OutPkts; /* 0x7320 */
227 /* 0x7330-0x7360 RSRV */
229 u64 OutVLAN; /* 0x7370 */
230 u64 InUCastOctects; /* 0x7380 */
231 u64 OutUCastOctects; /* 0x7390 */
233 /* 0x73A0-0x73B0 RSRV */
235 u64 InBCastOctects; /* 0x73C0 */
236 u64 OutBCastOctects; /* 0x73D0 */
237 u64 InOctects; /* 0x73E0 */
238 u64 OutOctects; /* 0x73F0 */
285 u32 va_lo; /* VAdr[31:0] */
287 u32 pa_lo; /* PAdr[31:0] */
292 #define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0)
300 #define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0)
301 #define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0)
325 ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))
337 #define BDX_REGS_SIZE 0x1000
339 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
340 #define regTXD_CFG1_0 0x4000
341 #define regRXF_CFG1_0 0x4010
342 #define regRXD_CFG1_0 0x4020
343 #define regTXF_CFG1_0 0x4030
344 #define regTXD_CFG0_0 0x4040
345 #define regRXF_CFG0_0 0x4050
346 #define regRXD_CFG0_0 0x4060
347 #define regTXF_CFG0_0 0x4070
348 #define regTXD_WPTR_0 0x4080
349 #define regRXF_WPTR_0 0x4090
350 #define regRXD_WPTR_0 0x40A0
351 #define regTXF_WPTR_0 0x40B0
352 #define regTXD_RPTR_0 0x40C0
353 #define regRXF_RPTR_0 0x40D0
354 #define regRXD_RPTR_0 0x40E0
355 #define regTXF_RPTR_0 0x40F0
356 #define regTXF_RPTR_3 0x40FC
359 #define FW_VER 0x5010
360 #define SROM_VER 0x5020
361 #define FPGA_VER 0x5030
362 #define FPGA_SEED 0x5040
364 /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
366 #define regISR0 0x5100
369 #define regIMR0 0x5110
371 #define regRDINTCM0 0x5120
372 #define regRDINTCM2 0x5128
374 #define regTDINTCM0 0x5130
376 #define regISR_MSK0 0x5140
378 #define regINIT_SEMAPHORE 0x5170
379 #define regINIT_STATUS 0x5180
381 #define regMAC_LNK_STAT 0x0200
382 #define MAC_LINK_STAT 0x4 /* Link state */
384 #define regGMAC_RXF_A 0x1240
386 #define regUNC_MAC0_A 0x1250
387 #define regUNC_MAC1_A 0x1260
388 #define regUNC_MAC2_A 0x1270
390 #define regVLAN_0 0x1800
392 #define regMAX_FRAME_A 0x12C0
394 #define regRX_MAC_MCST0 0x1A80
395 #define regRX_MAC_MCST1 0x1A84
397 #define regRX_MCST_HASH0 0x1A00
400 #define regVPC 0x2300
401 #define regVIC 0x2320
402 #define regVGLB 0x2340
404 #define regCLKPLL 0x5000
407 #define regREVISION 0x6000
408 #define regSCRATCH 0x6004
409 #define regCTRLST 0x6008
410 #define regMAC_ADDR_0 0x600C
411 #define regMAC_ADDR_1 0x6010
412 #define regFRM_LENGTH 0x6014
413 #define regPAUSE_QUANT 0x6018
414 #define regRX_FIFO_SECTION 0x601C
415 #define regTX_FIFO_SECTION 0x6020
416 #define regRX_FULLNESS 0x6024
417 #define regTX_FULLNESS 0x6028
418 #define regHASHTABLE 0x602C
419 #define regMDIO_ST 0x6030
420 #define regMDIO_CTL 0x6034
421 #define regMDIO_DATA 0x6038
422 #define regMDIO_ADDR 0x603C
424 #define regRST_PORT 0x7000
425 #define regDIS_PORT 0x7010
426 #define regRST_QU 0x7020
427 #define regDIS_QU 0x7030
429 #define regCTRLST_TX_ENA 0x0001
430 #define regCTRLST_RX_ENA 0x0002
431 #define regCTRLST_PRM_ENA 0x0010
432 #define regCTRLST_PAD_ENA 0x0020
436 #define regRX_FLT 0x1400
438 /* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/
439 #define TX_RX_CFG1_BASE 0xffffffff /*0-31 */
440 #define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */
441 #define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */
442 #define TX_RX_CFG0_SIZE 0x0003 /*1:0 */
444 /* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */
445 #define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */
447 /* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */
448 #define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */
450 #define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped
453 /* regISR 0x0100 */
454 /* regIMR 0x0110 */
455 #define IMR_INPROG 0x80000000 /*31 */
456 #define IR_LNKCHG1 0x10000000 /*28 */
457 #define IR_LNKCHG0 0x08000000 /*27 */
458 #define IR_GPIO 0x04000000 /*26 */
459 #define IR_RFRSH 0x02000000 /*25 */
460 #define IR_RSVD 0x01000000 /*24 */
461 #define IR_SWI 0x00800000 /*23 */
462 #define IR_RX_FREE_3 0x00400000 /*22 */
463 #define IR_RX_FREE_2 0x00200000 /*21 */
464 #define IR_RX_FREE_1 0x00100000 /*20 */
465 #define IR_RX_FREE_0 0x00080000 /*19 */
466 #define IR_TX_FREE_3 0x00040000 /*18 */
467 #define IR_TX_FREE_2 0x00020000 /*17 */
468 #define IR_TX_FREE_1 0x00010000 /*16 */
469 #define IR_TX_FREE_0 0x00008000 /*15 */
470 #define IR_RX_DESC_3 0x00004000 /*14 */
471 #define IR_RX_DESC_2 0x00002000 /*13 */
472 #define IR_RX_DESC_1 0x00001000 /*12 */
473 #define IR_RX_DESC_0 0x00000800 /*11 */
474 #define IR_PSE 0x00000400 /*10 */
475 #define IR_TMR3 0x00000200 /*9 */
476 #define IR_TMR2 0x00000100 /*8 */
477 #define IR_TMR1 0x00000080 /*7 */
478 #define IR_TMR0 0x00000040 /*6 */
479 #define IR_VNT 0x00000020 /*5 */
480 #define IR_RxFL 0x00000010 /*4 */
481 #define IR_SDPERR 0x00000008 /*3 */
482 #define IR_TR 0x00000004 /*2 */
483 #define IR_PCIE_LINK 0x00000002 /*1 */
484 #define IR_PCIE_TOUT 0x00000001 /*0 */
489 #define IR_ALL 0xfdfffff7
493 #define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */
494 #define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */
495 #define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */
496 #define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */
497 #define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */
498 #define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */
499 #define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */
500 #define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */
501 #define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */
502 #define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */
503 #define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */
505 #define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */
507 #define CLKPLL_PLLLKD 0x0200 /*9 */
508 #define CLKPLL_RSTEND 0x0100 /*8 */
509 #define CLKPLL_SFTRST 0x0001 /*0 */
514 * PCI-E Device Control Register (Offset 0x88)
517 #define PCI_DEV_CTRL_REG 0x88
522 * PCI-E Link Status Register (Offset 0x92)
525 #define PCI_LINK_STATUS_REG 0x92
540 } while (0)
546 } while (0)
551 #define ENTER do { } while (0)
555 if (0) \
557 } while (0)