Home
last modified time | relevance | path

Searched +full:0 +full:x36000 (Results 1 – 25 of 44) sorted by relevance

12

/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dgoya_blocks.h16 #define mmPCI_NRTR_BASE 0x7FFC000000ull
17 #define PCI_NRTR_MAX_OFFSET 0x608
18 #define PCI_NRTR_SECTION 0x4000
19 #define mmPCI_RD_REGULATOR_BASE 0x7FFC004000ull
20 #define PCI_RD_REGULATOR_MAX_OFFSET 0x74
21 #define PCI_RD_REGULATOR_SECTION 0x1000
22 #define mmPCI_WR_REGULATOR_BASE 0x7FFC005000ull
23 #define PCI_WR_REGULATOR_MAX_OFFSET 0x74
24 #define PCI_WR_REGULATOR_SECTION 0x3B000
25 #define mmMME1_RTR_BASE 0x7FFC040000ull
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Damlogic,g12a-usb2-phy.yaml37 const: 0
75 reg = <0x36000 0x2000>;
80 #phy-cells = <0>;
/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dbrcm,b53.yaml144 #size-cells = <0>;
152 #size-cells = <0>;
154 port@0 {
155 reg = <0>;
196 reg = <0x36000 0x1000>,
197 <0x3f308 0x8>,
198 <0x3f410 0xc>;
229 #size-cells = <0>;
231 port@0 {
233 reg = <0>;
/linux-6.12.1/sound/soc/mediatek/mt8365/
Dmt8365-afe-common.h121 MT8365_AFE_APLL1 = 0,
127 MT8365_AFE_1ST_I2S = 0,
133 MT8365_AFE_I2S_SEPARATE_CLOCK = 0,
138 MT8365_AFE_TDM_OUT_I2S = 0,
144 AFE_TDM_CH_START_O28_O29 = 0,
152 MT8365_PCM_FORMAT_I2S = 0,
159 MT8365_FS_8K = 0,
177 FS_8000HZ = 0, /* 0000b */
205 MT8365_AFE_IRQ_DIR_MCU = 0,
212 MT8365_I2S0_MCK = 0,
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi/asic_reg/
Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_7_0_sm8350.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x290,
39 .base = 0x16000, .len = 0x290,
44 .base = 0x17000, .len = 0x290,
49 .base = 0x18000, .len = 0x290,
54 .base = 0x19000, .len = 0x290,
59 .base = 0x1a000, .len = 0x290,
68 .base = 0x4000, .len = 0x344,
[all …]
Ddpu_10_0_sm8650.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x1000,
39 .base = 0x16000, .len = 0x1000,
44 .base = 0x17000, .len = 0x1000,
49 .base = 0x18000, .len = 0x1000,
54 .base = 0x19000, .len = 0x1000,
59 .base = 0x1a000, .len = 0x1000,
68 .base = 0x4000, .len = 0x344,
[all …]
Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
33 .base = 0x15000, .len = 0x290,
38 .base = 0x16000, .len = 0x290,
43 .base = 0x17000, .len = 0x290,
48 .base = 0x18000, .len = 0x290,
53 .base = 0x19000, .len = 0x290,
58 .base = 0x1a000, .len = 0x290,
67 .base = 0x4000, .len = 0x344,
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath10k/
Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
16 segment@0 { /* 0x4a000000 */
20 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/linux-6.12.1/sound/soc/mediatek/mt8186/
Dmt8186-dai-i2s.c17 I2S_FMT_EIAJ = 0,
22 I2S_WLEN_16_BIT = 0,
27 I2S_HD_NORMAL = 0,
32 I2S1_SEL_O28_O29 = 0,
37 I2S_IN_PAD_CONNSYS = 0,
79 if (strncmp(name, "I2S0", 4) == 0) in get_i2s_id_by_name()
81 else if (strncmp(name, "I2S1", 4) == 0) in get_i2s_id_by_name()
83 else if (strncmp(name, "I2S2", 4) == 0) in get_i2s_id_by_name()
85 else if (strncmp(name, "I2S3", 4) == 0) in get_i2s_id_by_name()
97 if (dai_id < 0) in get_i2s_priv_by_name()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12-common.dtsi107 reg = <0x0 0x05000000 0x0 0x300000>;
113 reg = <0x0 0x05300000 0x0 0x2000000>;
120 size = <0x0 0x10000000>;
121 alignment = <0x0 0x400000>;
138 reg = <0x0 0xfc000000 0x0 0x400000>,
139 <0x0 0xff648000 0x0 0x2000>,
140 <0x0 0xfc400000 0x0 0x200000>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
146 bus-range = <0x0 0xff>;
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dgcc-sm4450.c52 { 249600000, 2020000000, 0 },
56 .offset = 0x0,
59 .enable_reg = 0x62018,
60 .enable_mask = BIT(0),
73 { 0x1, 2 },
78 .offset = 0x0,
95 { 0x2, 3 },
100 .offset = 0x0,
117 .offset = 0x1000,
120 .enable_reg = 0x62018,
[all …]
Dgcc-qcm2290.c46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
Dgcc-sm8450.c40 .offset = 0x0,
43 .enable_reg = 0x62018,
44 .enable_mask = BIT(0),
57 { 0x1, 2 },
62 .offset = 0x0,
79 .offset = 0x4000,
82 .enable_reg = 0x62018,
96 .offset = 0x9000,
99 .enable_reg = 0x62018,
113 { P_BI_TCXO, 0 },
[all …]
Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
Dgcc-sm8250.c36 .offset = 0x0,
39 .enable_reg = 0x52018,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 .offset = 0x76000,
78 .enable_reg = 0x52018,
92 .offset = 0x1c000,
95 .enable_reg = 0x52018,
109 { P_BI_TCXO, 0 },
[all …]

12