Lines Matching +full:0 +full:x36000
52 { 249600000, 2020000000, 0 },
56 .offset = 0x0,
59 .enable_reg = 0x62018,
60 .enable_mask = BIT(0),
73 { 0x1, 2 },
78 .offset = 0x0,
95 { 0x2, 3 },
100 .offset = 0x0,
117 .offset = 0x1000,
120 .enable_reg = 0x62018,
134 .l = 0x14,
135 .alpha = 0xd555,
136 .config_ctl_val = 0x20485699,
137 .config_ctl_hi_val = 0x00182261,
138 .config_ctl_hi1_val = 0x32aa299c,
139 .user_ctl_val = 0x00000000,
140 .user_ctl_hi_val = 0x00000805,
144 .offset = 0x3000,
149 .enable_reg = 0x62018,
163 .offset = 0x4000,
166 .enable_reg = 0x62018,
180 .offset = 0x9000,
183 .enable_reg = 0x62018,
197 .offset = 0xa000,
200 .enable_reg = 0x62018,
214 { P_BI_TCXO, 0 },
226 { P_BI_TCXO, 0 },
240 { P_BI_TCXO, 0 },
256 { P_BI_TCXO, 0 },
266 { P_BI_TCXO, 0 },
282 { P_BI_TCXO, 0 },
290 { P_BI_TCXO, 0 },
306 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
316 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
326 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
336 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
346 { P_BI_TCXO, 0 },
358 .reg = 0x7b060,
372 .reg = 0x87060,
373 .shift = 0,
387 .reg = 0x870d0,
388 .shift = 0,
402 .reg = 0x87050,
403 .shift = 0,
417 .reg = 0x49068,
418 .shift = 0,
432 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
433 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
434 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
439 .cmd_rcgr = 0x74004,
454 .cmd_rcgr = 0x75004,
469 .cmd_rcgr = 0x76004,
484 F(9600000, P_BI_TCXO, 2, 0, 0),
485 F(19200000, P_BI_TCXO, 1, 0, 0),
490 .cmd_rcgr = 0x7b064,
505 F(19200000, P_BI_TCXO, 1, 0, 0),
506 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
511 .cmd_rcgr = 0x7b048,
512 .mnd_width = 0,
526 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
531 .cmd_rcgr = 0x43010,
532 .mnd_width = 0,
548 F(19200000, P_BI_TCXO, 1, 0, 0),
553 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
556 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
560 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
573 .cmd_rcgr = 0x27014,
584 F(19200000, P_BI_TCXO, 1, 0, 0),
589 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
592 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
605 .cmd_rcgr = 0x27148,
622 .cmd_rcgr = 0x2727c,
639 .cmd_rcgr = 0x273b0,
656 .cmd_rcgr = 0x274e4,
673 .cmd_rcgr = 0x28014,
690 .cmd_rcgr = 0x28148,
707 .cmd_rcgr = 0x2827c,
724 .cmd_rcgr = 0x283b0,
741 .cmd_rcgr = 0x284e4,
753 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
754 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
755 F(100000000, P_GCC_GPLL0_OUT_ODD, 2, 0, 0),
756 F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
757 F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
762 .cmd_rcgr = 0xb3010,
777 F(100000000, P_GCC_GPLL0_OUT_ODD, 2, 0, 0),
778 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
779 F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
784 .cmd_rcgr = 0xb3030,
785 .mnd_width = 0,
800 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
801 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
802 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
803 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
808 .cmd_rcgr = 0x24014,
823 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
824 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
825 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
826 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
831 .cmd_rcgr = 0x8702c,
846 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
847 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
848 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
853 .cmd_rcgr = 0x87074,
854 .mnd_width = 0,
868 .cmd_rcgr = 0x870a8,
869 .mnd_width = 0,
883 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
884 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
885 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
890 .cmd_rcgr = 0x8708c,
891 .mnd_width = 0,
905 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
906 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
907 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
908 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
913 .cmd_rcgr = 0x49028,
928 F(19200000, P_BI_TCXO, 1, 0, 0),
933 .cmd_rcgr = 0x49040,
934 .mnd_width = 0,
948 .cmd_rcgr = 0x4906c,
949 .mnd_width = 0,
963 F(133333333, P_GCC_GPLL3_OUT_MAIN, 3, 0, 0),
964 F(240000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),
965 F(365000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),
966 F(384000000, P_GCC_GPLL3_OUT_MAIN, 2, 0, 0),
971 .cmd_rcgr = 0xb6004,
972 .mnd_width = 0,
986 .reg = 0x7b084,
987 .shift = 0,
1001 .reg = 0x49058,
1002 .shift = 0,
1016 .halt_reg = 0x7b08c,
1018 .hwcg_reg = 0x7b08c,
1021 .enable_reg = 0x62000,
1031 .halt_reg = 0x870d4,
1033 .hwcg_reg = 0x870d4,
1036 .enable_reg = 0x870d4,
1037 .enable_mask = BIT(0),
1051 .halt_reg = 0x870d4,
1053 .hwcg_reg = 0x870d4,
1056 .enable_reg = 0x870d4,
1071 .halt_reg = 0x49088,
1073 .hwcg_reg = 0x49088,
1076 .enable_reg = 0x49088,
1077 .enable_mask = BIT(0),
1091 .halt_reg = 0x48004,
1093 .hwcg_reg = 0x48004,
1096 .enable_reg = 0x62000,
1106 .halt_reg = 0x36010,
1108 .hwcg_reg = 0x36010,
1111 .enable_reg = 0x36010,
1112 .enable_mask = BIT(0),
1121 .halt_reg = 0x36014,
1123 .hwcg_reg = 0x36014,
1126 .enable_reg = 0x36014,
1127 .enable_mask = BIT(0),
1136 .halt_reg = 0x20030,
1138 .hwcg_reg = 0x20030,
1141 .enable_reg = 0x62000,
1151 .halt_reg = 0x49084,
1153 .hwcg_reg = 0x49084,
1156 .enable_reg = 0x49084,
1157 .enable_mask = BIT(0),
1171 .halt_reg = 0x81154,
1173 .hwcg_reg = 0x81154,
1176 .enable_reg = 0x81154,
1177 .enable_mask = BIT(0),
1186 .halt_reg = 0x7b090,
1188 .hwcg_reg = 0x7b090,
1191 .enable_reg = 0x62000,
1201 .halt_reg = 0x3700c,
1203 .hwcg_reg = 0x3700c,
1206 .enable_reg = 0x3700c,
1207 .enable_mask = BIT(0),
1216 .halt_reg = 0x9c00c,
1219 .enable_reg = 0x9c00c,
1220 .enable_mask = BIT(0),
1229 .halt_reg = 0x74000,
1232 .enable_reg = 0x74000,
1233 .enable_mask = BIT(0),
1247 .halt_reg = 0x75000,
1250 .enable_reg = 0x75000,
1251 .enable_mask = BIT(0),
1265 .halt_reg = 0x76000,
1268 .enable_reg = 0x76000,
1269 .enable_mask = BIT(0),
1285 .enable_reg = 0x62000,
1302 .enable_reg = 0x62000,
1317 .halt_reg = 0x81010,
1319 .hwcg_reg = 0x81010,
1322 .enable_reg = 0x81010,
1323 .enable_mask = BIT(0),
1332 .halt_reg = 0x81018,
1335 .enable_reg = 0x81018,
1336 .enable_mask = BIT(0),
1345 .halt_reg = 0x8d004,
1348 .enable_reg = 0x8d004,
1349 .enable_mask = BIT(0),
1358 .halt_reg = 0x8d010,
1361 .enable_reg = 0x8d010,
1362 .enable_mask = BIT(0),
1371 .halt_reg = 0x8d008,
1374 .enable_reg = 0x8d008,
1375 .enable_mask = BIT(0),
1384 .halt_reg = 0x8d00c,
1387 .enable_reg = 0x8d00c,
1388 .enable_mask = BIT(0),
1397 .halt_reg = 0x8d018,
1400 .enable_reg = 0x8d018,
1401 .enable_mask = BIT(0),
1410 .halt_reg = 0x8d01c,
1413 .enable_reg = 0x8d01c,
1414 .enable_mask = BIT(0),
1423 .halt_reg = 0x8d014,
1426 .enable_reg = 0x8d014,
1427 .enable_mask = BIT(0),
1436 .halt_reg = 0x8d02c,
1439 .enable_reg = 0x8d02c,
1440 .enable_mask = BIT(0),
1449 .halt_reg = 0x7b034,
1452 .enable_reg = 0x62008,
1467 .halt_reg = 0x7b030,
1469 .hwcg_reg = 0x7b030,
1472 .enable_reg = 0x62008,
1482 .halt_reg = 0x9c004,
1485 .enable_reg = 0x9c004,
1486 .enable_mask = BIT(0),
1495 .halt_reg = 0x7b028,
1498 .enable_reg = 0x62008,
1508 .halt_reg = 0x7b044,
1511 .enable_reg = 0x62000,
1526 .halt_reg = 0x7b03c,
1529 .enable_reg = 0x62008,
1544 .halt_reg = 0x7b094,
1547 .enable_reg = 0x62010,
1562 .halt_reg = 0x7b020,
1564 .hwcg_reg = 0x7b020,
1567 .enable_reg = 0x62008,
1568 .enable_mask = BIT(0),
1577 .halt_reg = 0x7b01c,
1580 .enable_reg = 0x62008,
1590 .halt_reg = 0x4300c,
1593 .enable_reg = 0x4300c,
1594 .enable_mask = BIT(0),
1608 .halt_reg = 0x43004,
1610 .hwcg_reg = 0x43004,
1613 .enable_reg = 0x43004,
1614 .enable_mask = BIT(0),
1623 .halt_reg = 0x43008,
1626 .enable_reg = 0x43008,
1627 .enable_mask = BIT(0),
1636 .halt_reg = 0x36008,
1638 .hwcg_reg = 0x36008,
1641 .enable_reg = 0x36008,
1642 .enable_mask = BIT(0),
1651 .halt_reg = 0x3600c,
1653 .hwcg_reg = 0x3600c,
1656 .enable_reg = 0x3600c,
1657 .enable_mask = BIT(0),
1666 .halt_reg = 0x37008,
1668 .hwcg_reg = 0x37008,
1671 .enable_reg = 0x37008,
1672 .enable_mask = BIT(0),
1681 .halt_reg = 0x81008,
1683 .hwcg_reg = 0x81008,
1686 .enable_reg = 0x81008,
1687 .enable_mask = BIT(0),
1696 .halt_reg = 0x7b018,
1698 .hwcg_reg = 0x7b018,
1701 .enable_reg = 0x7b018,
1702 .enable_mask = BIT(0),
1711 .halt_reg = 0x42008,
1713 .hwcg_reg = 0x42008,
1716 .enable_reg = 0x42008,
1717 .enable_mask = BIT(0),
1726 .halt_reg = 0x3300c,
1729 .enable_reg = 0x62008,
1739 .halt_reg = 0x33000,
1742 .enable_reg = 0x62008,
1752 .halt_reg = 0x2700c,
1755 .enable_reg = 0x62008,
1770 .halt_reg = 0x27140,
1773 .enable_reg = 0x62008,
1788 .halt_reg = 0x27274,
1791 .enable_reg = 0x62008,
1806 .halt_reg = 0x273a8,
1809 .enable_reg = 0x62008,
1824 .halt_reg = 0x274dc,
1827 .enable_reg = 0x62008,
1842 .halt_reg = 0x3314c,
1845 .enable_reg = 0x62008,
1855 .halt_reg = 0x33140,
1858 .enable_reg = 0x62008,
1868 .halt_reg = 0x2800c,
1871 .enable_reg = 0x62008,
1886 .halt_reg = 0x28140,
1889 .enable_reg = 0x62008,
1904 .halt_reg = 0x28274,
1907 .enable_reg = 0x62008,
1922 .halt_reg = 0x283a8,
1925 .enable_reg = 0x62008,
1940 .halt_reg = 0x284dc,
1943 .enable_reg = 0x62008,
1958 .halt_reg = 0x27004,
1960 .hwcg_reg = 0x27004,
1963 .enable_reg = 0x62008,
1973 .halt_reg = 0x27008,
1975 .hwcg_reg = 0x27008,
1978 .enable_reg = 0x62008,
1988 .halt_reg = 0x28004,
1990 .hwcg_reg = 0x28004,
1993 .enable_reg = 0x62008,
2003 .halt_reg = 0x28008,
2005 .hwcg_reg = 0x28008,
2008 .enable_reg = 0x62008,
2018 .halt_reg = 0xb3004,
2021 .enable_reg = 0xb3004,
2022 .enable_mask = BIT(0),
2031 .halt_reg = 0xb3008,
2034 .enable_reg = 0xb3008,
2035 .enable_mask = BIT(0),
2049 .halt_reg = 0xb3028,
2051 .hwcg_reg = 0xb3028,
2054 .enable_reg = 0xb3028,
2055 .enable_mask = BIT(0),
2069 .halt_reg = 0x2400c,
2072 .enable_reg = 0x2400c,
2073 .enable_mask = BIT(0),
2082 .halt_reg = 0x24004,
2085 .enable_reg = 0x24004,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x9c000,
2103 .enable_reg = 0x9c000,
2104 .enable_mask = BIT(0),
2113 .halt_reg = 0x9c024,
2116 .enable_reg = 0x9c024,
2117 .enable_mask = BIT(0),
2126 .halt_reg = 0x87020,
2128 .hwcg_reg = 0x87020,
2131 .enable_reg = 0x87020,
2132 .enable_mask = BIT(0),
2141 .halt_reg = 0x87018,
2143 .hwcg_reg = 0x87018,
2146 .enable_reg = 0x87018,
2147 .enable_mask = BIT(0),
2161 .halt_reg = 0x87018,
2163 .hwcg_reg = 0x87018,
2166 .enable_reg = 0x87018,
2181 .halt_reg = 0x8706c,
2183 .hwcg_reg = 0x8706c,
2186 .enable_reg = 0x8706c,
2187 .enable_mask = BIT(0),
2201 .halt_reg = 0x8706c,
2203 .hwcg_reg = 0x8706c,
2206 .enable_reg = 0x8706c,
2221 .halt_reg = 0x870a4,
2223 .hwcg_reg = 0x870a4,
2226 .enable_reg = 0x870a4,
2227 .enable_mask = BIT(0),
2241 .halt_reg = 0x870a4,
2243 .hwcg_reg = 0x870a4,
2246 .enable_reg = 0x870a4,
2261 .halt_reg = 0x87028,
2264 .enable_reg = 0x87028,
2265 .enable_mask = BIT(0),
2279 .halt_reg = 0x870c0,
2282 .enable_reg = 0x870c0,
2283 .enable_mask = BIT(0),
2297 .halt_reg = 0x87024,
2300 .enable_reg = 0x87024,
2301 .enable_mask = BIT(0),
2315 .halt_reg = 0x87064,
2317 .hwcg_reg = 0x87064,
2320 .enable_reg = 0x87064,
2321 .enable_mask = BIT(0),
2335 .halt_reg = 0x87064,
2337 .hwcg_reg = 0x87064,
2340 .enable_reg = 0x87064,
2355 .halt_reg = 0x49018,
2358 .enable_reg = 0x49018,
2359 .enable_mask = BIT(0),
2373 .halt_reg = 0x49024,
2376 .enable_reg = 0x49024,
2377 .enable_mask = BIT(0),
2391 .halt_reg = 0x49020,
2394 .enable_reg = 0x49020,
2395 .enable_mask = BIT(0),
2404 .halt_reg = 0x9c010,
2407 .enable_reg = 0x9c010,
2408 .enable_mask = BIT(0),
2417 .halt_reg = 0x4905c,
2420 .enable_reg = 0x4905c,
2421 .enable_mask = BIT(0),
2435 .halt_reg = 0x49060,
2438 .enable_reg = 0x49060,
2439 .enable_mask = BIT(0),
2453 .halt_reg = 0x49064,
2455 .hwcg_reg = 0x49064,
2458 .enable_reg = 0x49064,
2459 .enable_mask = BIT(0),
2473 .halt_reg = 0x42020,
2475 .hwcg_reg = 0x42020,
2478 .enable_reg = 0x42020,
2479 .enable_mask = BIT(0),
2488 .halt_reg = 0x4201c,
2491 .enable_reg = 0x4201c,
2492 .enable_mask = BIT(0),
2501 .halt_reg = 0x42014,
2503 .hwcg_reg = 0x42014,
2506 .enable_reg = 0x42014,
2507 .enable_mask = BIT(0),
2516 .halt_reg = 0xb6058,
2518 .hwcg_reg = 0xb6058,
2521 .enable_reg = 0xb6058,
2522 .enable_mask = BIT(0),
2536 .halt_reg = 0xb6038,
2539 .enable_reg = 0xb6038,
2540 .enable_mask = BIT(0),
2554 .gdscr = 0x7b004,
2555 .en_rest_wait_val = 0x2,
2556 .en_few_wait_val = 0x2,
2557 .clk_dis_wait_val = 0xf,
2566 .gdscr = 0x87004,
2567 .en_rest_wait_val = 0x2,
2568 .en_few_wait_val = 0x2,
2569 .clk_dis_wait_val = 0xf,
2578 .gdscr = 0x49004,
2579 .en_rest_wait_val = 0x2,
2580 .en_few_wait_val = 0x2,
2581 .clk_dis_wait_val = 0xf,
2590 .gdscr = 0xb6044,
2591 .en_rest_wait_val = 0x2,
2592 .en_few_wait_val = 0x2,
2593 .clk_dis_wait_val = 0xf,
2602 .gdscr = 0xb6020,
2603 .en_rest_wait_val = 0x2,
2604 .en_few_wait_val = 0x2,
2605 .clk_dis_wait_val = 0xf,
2764 [GCC_CAMERA_BCR] = { 0x36000 },
2765 [GCC_DISPLAY_BCR] = { 0x37000 },
2766 [GCC_GPU_BCR] = { 0x81000 },
2767 [GCC_PCIE_0_BCR] = { 0x7b000 },
2768 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
2769 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
2770 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
2771 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
2772 [GCC_PCIE_PHY_BCR] = { 0x7f000 },
2773 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
2774 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
2775 [GCC_PDM_BCR] = { 0x43000 },
2776 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
2777 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
2778 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
2779 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
2780 [GCC_SDCC1_BCR] = { 0xb3000 },
2781 [GCC_SDCC2_BCR] = { 0x24000 },
2782 [GCC_UFS_PHY_BCR] = { 0x87000 },
2783 [GCC_USB30_PRIM_BCR] = { 0x49000 },
2784 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
2785 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
2786 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
2787 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
2788 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
2789 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
2790 [GCC_VCODEC0_BCR] = { 0xb6040 },
2791 [GCC_VENUS_BCR] = { 0xb601c },
2792 [GCC_VIDEO_BCR] = { 0x42000 },
2793 [GCC_VIDEO_VENUS_BCR] = { 0xb6000 },
2794 [GCC_VENUS_CTL_AXI_CLK_ARES] = { .reg = 0x4201c, .bit = 2, .udelay = 400 },
2795 [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { .reg = 0xb6038, .bit = 2, .udelay = 400 },
2815 .max_register = 0x1f41f0,
2853 qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ in gcc_sm4450_probe()
2854 qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */ in gcc_sm4450_probe()
2855 qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */ in gcc_sm4450_probe()
2856 qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ in gcc_sm4450_probe()
2857 qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */ in gcc_sm4450_probe()
2858 qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sm4450_probe()
2859 qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ in gcc_sm4450_probe()
2860 qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */ in gcc_sm4450_probe()
2862 regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); in gcc_sm4450_probe()