Lines Matching +full:0 +full:x36000
40 .offset = 0x0,
43 .enable_reg = 0x62018,
44 .enable_mask = BIT(0),
57 { 0x1, 2 },
62 .offset = 0x0,
79 .offset = 0x4000,
82 .enable_reg = 0x62018,
96 .offset = 0x9000,
99 .enable_reg = 0x62018,
113 { P_BI_TCXO, 0 },
125 { P_BI_TCXO, 0 },
139 { P_BI_TCXO, 0 },
149 { P_BI_TCXO, 0 },
157 { P_PCIE_1_PHY_AUX_CLK, 0 },
167 { P_BI_TCXO, 0 },
183 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
193 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
203 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
213 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
223 .reg = 0x7b060,
237 .reg = 0x9d080,
238 .shift = 0,
252 .reg = 0x9d064,
266 .reg = 0x87060,
267 .shift = 0,
281 .reg = 0x870d0,
282 .shift = 0,
296 .reg = 0x87050,
297 .shift = 0,
311 .reg = 0x49068,
312 .shift = 0,
326 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
327 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
328 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
333 .cmd_rcgr = 0x74004,
349 .cmd_rcgr = 0x75004,
365 .cmd_rcgr = 0x76004,
381 F(19200000, P_BI_TCXO, 1, 0, 0),
386 .cmd_rcgr = 0x7b064,
402 F(19200000, P_BI_TCXO, 1, 0, 0),
403 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
408 .cmd_rcgr = 0x7b048,
409 .mnd_width = 0,
424 .cmd_rcgr = 0x9d068,
440 .cmd_rcgr = 0x9d04c,
441 .mnd_width = 0,
456 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
461 .cmd_rcgr = 0x43010,
462 .mnd_width = 0,
479 F(19200000, P_BI_TCXO, 1, 0, 0),
484 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
487 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
500 .cmd_rcgr = 0x27014,
518 .cmd_rcgr = 0x27148,
536 .cmd_rcgr = 0x2727c,
554 .cmd_rcgr = 0x273b0,
572 .cmd_rcgr = 0x274e4,
584 F(19200000, P_BI_TCXO, 1, 0, 0),
587 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
589 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
602 .cmd_rcgr = 0x27618,
620 .cmd_rcgr = 0x2774c,
638 .cmd_rcgr = 0x27880,
650 F(19200000, P_BI_TCXO, 1, 0, 0),
655 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
658 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
662 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
675 .cmd_rcgr = 0x28014,
693 .cmd_rcgr = 0x28148,
711 .cmd_rcgr = 0x2827c,
729 .cmd_rcgr = 0x283b0,
747 .cmd_rcgr = 0x284e4,
765 .cmd_rcgr = 0x28618,
783 .cmd_rcgr = 0x2874c,
801 .cmd_rcgr = 0x2e014,
819 .cmd_rcgr = 0x2e148,
837 .cmd_rcgr = 0x2e27c,
855 .cmd_rcgr = 0x2e3b0,
873 .cmd_rcgr = 0x2e4e4,
891 .cmd_rcgr = 0x2e618,
909 .cmd_rcgr = 0x2e74c,
920 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
921 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
922 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
923 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
928 .cmd_rcgr = 0x24014,
945 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
946 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
951 .cmd_rcgr = 0x26014,
967 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
968 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
969 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
970 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
975 .cmd_rcgr = 0x8702c,
991 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
992 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
993 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
998 .cmd_rcgr = 0x87074,
999 .mnd_width = 0,
1014 F(9600000, P_BI_TCXO, 2, 0, 0),
1015 F(19200000, P_BI_TCXO, 1, 0, 0),
1020 .cmd_rcgr = 0x870a8,
1021 .mnd_width = 0,
1036 .cmd_rcgr = 0x8708c,
1037 .mnd_width = 0,
1052 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1053 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1054 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1055 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1060 .cmd_rcgr = 0x49028,
1076 .cmd_rcgr = 0x49040,
1077 .mnd_width = 0,
1092 .cmd_rcgr = 0x4906c,
1093 .mnd_width = 0,
1108 .reg = 0x49058,
1109 .shift = 0,
1123 .halt_reg = 0x7b08c,
1125 .hwcg_reg = 0x7b08c,
1128 .enable_reg = 0x62000,
1138 .halt_reg = 0x9d098,
1140 .hwcg_reg = 0x9d098,
1143 .enable_reg = 0x62000,
1153 .halt_reg = 0x870d4,
1155 .hwcg_reg = 0x870d4,
1158 .enable_reg = 0x870d4,
1159 .enable_mask = BIT(0),
1173 .halt_reg = 0x870d4,
1175 .hwcg_reg = 0x870d4,
1178 .enable_reg = 0x870d4,
1193 .halt_reg = 0x49088,
1195 .hwcg_reg = 0x49088,
1198 .enable_reg = 0x49088,
1199 .enable_mask = BIT(0),
1213 .halt_reg = 0x48004,
1215 .hwcg_reg = 0x48004,
1218 .enable_reg = 0x62000,
1228 .halt_reg = 0x36010,
1230 .hwcg_reg = 0x36010,
1233 .enable_reg = 0x36010,
1234 .enable_mask = BIT(0),
1243 .halt_reg = 0x36018,
1245 .hwcg_reg = 0x36018,
1248 .enable_reg = 0x36018,
1249 .enable_mask = BIT(0),
1258 .halt_reg = 0x20030,
1260 .hwcg_reg = 0x20030,
1263 .enable_reg = 0x62000,
1273 .halt_reg = 0x49084,
1275 .hwcg_reg = 0x49084,
1278 .enable_reg = 0x49084,
1279 .enable_mask = BIT(0),
1293 .halt_reg = 0x81154,
1295 .hwcg_reg = 0x81154,
1298 .enable_reg = 0x81154,
1299 .enable_mask = BIT(0),
1308 .halt_reg = 0x9d094,
1310 .hwcg_reg = 0x9d094,
1313 .enable_reg = 0x62000,
1323 .halt_reg = 0x3700c,
1325 .hwcg_reg = 0x3700c,
1328 .enable_reg = 0x3700c,
1329 .enable_mask = BIT(0),
1338 .halt_reg = 0x37014,
1340 .hwcg_reg = 0x37014,
1343 .enable_reg = 0x37014,
1344 .enable_mask = BIT(0),
1353 .halt_reg = 0x9c00c,
1356 .enable_reg = 0x9c00c,
1357 .enable_mask = BIT(0),
1366 .halt_reg = 0x74000,
1369 .enable_reg = 0x74000,
1370 .enable_mask = BIT(0),
1384 .halt_reg = 0x75000,
1387 .enable_reg = 0x75000,
1388 .enable_mask = BIT(0),
1402 .halt_reg = 0x76000,
1405 .enable_reg = 0x76000,
1406 .enable_mask = BIT(0),
1422 .enable_reg = 0x62000,
1439 .enable_reg = 0x62000,
1454 .halt_reg = 0x81010,
1456 .hwcg_reg = 0x81010,
1459 .enable_reg = 0x81010,
1460 .enable_mask = BIT(0),
1469 .halt_reg = 0x81018,
1472 .enable_reg = 0x81018,
1473 .enable_mask = BIT(0),
1482 .halt_reg = 0x7b034,
1485 .enable_reg = 0x62008,
1500 .halt_reg = 0x7b030,
1502 .hwcg_reg = 0x7b030,
1505 .enable_reg = 0x62008,
1515 .halt_reg = 0x9c004,
1518 .enable_reg = 0x9c004,
1519 .enable_mask = BIT(0),
1528 .halt_reg = 0x7b028,
1531 .enable_reg = 0x62008,
1541 .halt_reg = 0x7b044,
1544 .enable_reg = 0x62000,
1559 .halt_reg = 0x7b03c,
1562 .enable_reg = 0x62008,
1577 .halt_reg = 0x7b020,
1579 .hwcg_reg = 0x7b020,
1582 .enable_reg = 0x62008,
1583 .enable_mask = BIT(0),
1592 .halt_reg = 0x7b01c,
1595 .enable_reg = 0x62008,
1605 .halt_reg = 0x9d030,
1608 .enable_reg = 0x62000,
1623 .halt_reg = 0x9d02c,
1625 .hwcg_reg = 0x9d02c,
1628 .enable_reg = 0x62000,
1638 .halt_reg = 0x9c008,
1641 .enable_reg = 0x9c008,
1642 .enable_mask = BIT(0),
1651 .halt_reg = 0x9d024,
1654 .enable_reg = 0x62000,
1664 .halt_reg = 0x9d038,
1667 .enable_reg = 0x62000,
1682 .halt_reg = 0x9d048,
1685 .enable_reg = 0x62000,
1700 .halt_reg = 0x9d040,
1703 .enable_reg = 0x62000,
1718 .halt_reg = 0x9d01c,
1720 .hwcg_reg = 0x9d01c,
1723 .enable_reg = 0x62000,
1733 .halt_reg = 0x9d018,
1736 .enable_reg = 0x62000,
1746 .halt_reg = 0x4300c,
1749 .enable_reg = 0x4300c,
1750 .enable_mask = BIT(0),
1764 .halt_reg = 0x43004,
1766 .hwcg_reg = 0x43004,
1769 .enable_reg = 0x43004,
1770 .enable_mask = BIT(0),
1779 .halt_reg = 0x43008,
1782 .enable_reg = 0x43008,
1783 .enable_mask = BIT(0),
1792 .halt_reg = 0x36008,
1794 .hwcg_reg = 0x36008,
1797 .enable_reg = 0x36008,
1798 .enable_mask = BIT(0),
1807 .halt_reg = 0x3600c,
1809 .hwcg_reg = 0x3600c,
1812 .enable_reg = 0x3600c,
1813 .enable_mask = BIT(0),
1822 .halt_reg = 0x37008,
1824 .hwcg_reg = 0x37008,
1827 .enable_reg = 0x37008,
1828 .enable_mask = BIT(0),
1837 .halt_reg = 0x81008,
1839 .hwcg_reg = 0x81008,
1842 .enable_reg = 0x81008,
1843 .enable_mask = BIT(0),
1852 .halt_reg = 0x7b018,
1854 .hwcg_reg = 0x7b018,
1857 .enable_reg = 0x7b018,
1858 .enable_mask = BIT(0),
1867 .halt_reg = 0x42014,
1869 .hwcg_reg = 0x42014,
1872 .enable_reg = 0x42014,
1873 .enable_mask = BIT(0),
1882 .halt_reg = 0x42008,
1884 .hwcg_reg = 0x42008,
1887 .enable_reg = 0x42008,
1888 .enable_mask = BIT(0),
1897 .halt_reg = 0x42010,
1899 .hwcg_reg = 0x42010,
1902 .enable_reg = 0x42010,
1903 .enable_mask = BIT(0),
1912 .halt_reg = 0x4200c,
1914 .hwcg_reg = 0x4200c,
1917 .enable_reg = 0x4200c,
1918 .enable_mask = BIT(0),
1927 .halt_reg = 0x3300c,
1930 .enable_reg = 0x62008,
1940 .halt_reg = 0x33000,
1943 .enable_reg = 0x62008,
1953 .halt_reg = 0x2700c,
1956 .enable_reg = 0x62008,
1971 .halt_reg = 0x27140,
1974 .enable_reg = 0x62008,
1989 .halt_reg = 0x27274,
1992 .enable_reg = 0x62008,
2007 .halt_reg = 0x273a8,
2010 .enable_reg = 0x62008,
2025 .halt_reg = 0x274dc,
2028 .enable_reg = 0x62008,
2043 .halt_reg = 0x27610,
2046 .enable_reg = 0x62008,
2061 .halt_reg = 0x27744,
2064 .enable_reg = 0x62008,
2079 .halt_reg = 0x27878,
2082 .enable_reg = 0x62008,
2097 .halt_reg = 0x3314c,
2100 .enable_reg = 0x62008,
2110 .halt_reg = 0x33140,
2113 .enable_reg = 0x62008,
2123 .halt_reg = 0x2800c,
2126 .enable_reg = 0x62008,
2141 .halt_reg = 0x28140,
2144 .enable_reg = 0x62008,
2159 .halt_reg = 0x28274,
2162 .enable_reg = 0x62008,
2177 .halt_reg = 0x283a8,
2180 .enable_reg = 0x62008,
2195 .halt_reg = 0x284dc,
2198 .enable_reg = 0x62008,
2213 .halt_reg = 0x28610,
2216 .enable_reg = 0x62008,
2231 .halt_reg = 0x28744,
2234 .enable_reg = 0x62008,
2249 .halt_reg = 0x3328c,
2252 .enable_reg = 0x62010,
2262 .halt_reg = 0x33280,
2265 .enable_reg = 0x62010,
2266 .enable_mask = BIT(0),
2275 .halt_reg = 0x2e00c,
2278 .enable_reg = 0x62010,
2293 .halt_reg = 0x2e140,
2296 .enable_reg = 0x62010,
2311 .halt_reg = 0x2e274,
2314 .enable_reg = 0x62010,
2329 .halt_reg = 0x2e3a8,
2332 .enable_reg = 0x62010,
2347 .halt_reg = 0x2e4dc,
2350 .enable_reg = 0x62010,
2365 .halt_reg = 0x2e610,
2368 .enable_reg = 0x62010,
2383 .halt_reg = 0x2e744,
2386 .enable_reg = 0x62010,
2401 .halt_reg = 0x27004,
2403 .hwcg_reg = 0x27004,
2406 .enable_reg = 0x62008,
2416 .halt_reg = 0x27008,
2418 .hwcg_reg = 0x27008,
2421 .enable_reg = 0x62008,
2431 .halt_reg = 0x28004,
2433 .hwcg_reg = 0x28004,
2436 .enable_reg = 0x62008,
2446 .halt_reg = 0x28008,
2448 .hwcg_reg = 0x28008,
2451 .enable_reg = 0x62008,
2461 .halt_reg = 0x2e004,
2463 .hwcg_reg = 0x2e004,
2466 .enable_reg = 0x62010,
2476 .halt_reg = 0x2e008,
2478 .hwcg_reg = 0x2e008,
2481 .enable_reg = 0x62010,
2491 .halt_reg = 0x2400c,
2494 .enable_reg = 0x2400c,
2495 .enable_mask = BIT(0),
2504 .halt_reg = 0x24004,
2507 .enable_reg = 0x24004,
2508 .enable_mask = BIT(0),
2522 .halt_reg = 0x24010,
2524 .hwcg_reg = 0x24010,
2527 .enable_reg = 0x24010,
2528 .enable_mask = BIT(0),
2537 .halt_reg = 0x2600c,
2540 .enable_reg = 0x2600c,
2541 .enable_mask = BIT(0),
2550 .halt_reg = 0x26004,
2553 .enable_reg = 0x26004,
2554 .enable_mask = BIT(0),
2568 .halt_reg = 0x26010,
2570 .hwcg_reg = 0x26010,
2573 .enable_reg = 0x26010,
2574 .enable_mask = BIT(0),
2583 .halt_reg = 0x9c000,
2586 .enable_reg = 0x9c000,
2587 .enable_mask = BIT(0),
2596 .halt_reg = 0x87020,
2598 .hwcg_reg = 0x87020,
2601 .enable_reg = 0x87020,
2602 .enable_mask = BIT(0),
2611 .halt_reg = 0x87018,
2613 .hwcg_reg = 0x87018,
2616 .enable_reg = 0x87018,
2617 .enable_mask = BIT(0),
2631 .halt_reg = 0x87018,
2633 .hwcg_reg = 0x87018,
2636 .enable_reg = 0x87018,
2651 .halt_reg = 0x8706c,
2653 .hwcg_reg = 0x8706c,
2656 .enable_reg = 0x8706c,
2657 .enable_mask = BIT(0),
2671 .halt_reg = 0x8706c,
2673 .hwcg_reg = 0x8706c,
2676 .enable_reg = 0x8706c,
2691 .halt_reg = 0x870a4,
2693 .hwcg_reg = 0x870a4,
2696 .enable_reg = 0x870a4,
2697 .enable_mask = BIT(0),
2711 .halt_reg = 0x870a4,
2713 .hwcg_reg = 0x870a4,
2716 .enable_reg = 0x870a4,
2731 .halt_reg = 0x87028,
2734 .enable_reg = 0x87028,
2735 .enable_mask = BIT(0),
2749 .halt_reg = 0x870c0,
2752 .enable_reg = 0x870c0,
2753 .enable_mask = BIT(0),
2767 .halt_reg = 0x87024,
2770 .enable_reg = 0x87024,
2771 .enable_mask = BIT(0),
2785 .halt_reg = 0x87064,
2787 .hwcg_reg = 0x87064,
2790 .enable_reg = 0x87064,
2791 .enable_mask = BIT(0),
2805 .halt_reg = 0x87064,
2807 .hwcg_reg = 0x87064,
2810 .enable_reg = 0x87064,
2825 .halt_reg = 0x49018,
2828 .enable_reg = 0x49018,
2829 .enable_mask = BIT(0),
2843 .halt_reg = 0x49024,
2846 .enable_reg = 0x49024,
2847 .enable_mask = BIT(0),
2861 .halt_reg = 0x49020,
2864 .enable_reg = 0x49020,
2865 .enable_mask = BIT(0),
2874 .halt_reg = 0x9c010,
2877 .enable_reg = 0x9c010,
2878 .enable_mask = BIT(0),
2887 .halt_reg = 0x4905c,
2890 .enable_reg = 0x4905c,
2891 .enable_mask = BIT(0),
2905 .halt_reg = 0x49060,
2908 .enable_reg = 0x49060,
2909 .enable_mask = BIT(0),
2923 .halt_reg = 0x49064,
2925 .hwcg_reg = 0x49064,
2928 .enable_reg = 0x49064,
2929 .enable_mask = BIT(0),
2943 .halt_reg = 0x42018,
2945 .hwcg_reg = 0x42018,
2948 .enable_reg = 0x42018,
2949 .enable_mask = BIT(0),
2958 .halt_reg = 0x42020,
2960 .hwcg_reg = 0x42020,
2963 .enable_reg = 0x42020,
2964 .enable_mask = BIT(0),
2973 .gdscr = 0x7b004,
2981 .gdscr = 0x9d004,
2989 .gdscr = 0x87004,
2997 .gdscr = 0x49004,
3172 [GCC_CAMERA_BCR] = { 0x36000 },
3173 [GCC_DISPLAY_BCR] = { 0x37000 },
3174 [GCC_GPU_BCR] = { 0x81000 },
3175 [GCC_PCIE_0_BCR] = { 0x7b000 },
3176 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
3177 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
3178 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
3179 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
3180 [GCC_PCIE_1_BCR] = { 0x9d000 },
3181 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
3182 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
3183 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
3184 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
3185 [GCC_PCIE_PHY_BCR] = { 0x7f000 },
3186 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
3187 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
3188 [GCC_PDM_BCR] = { 0x43000 },
3189 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
3190 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
3191 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
3192 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
3193 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
3194 [GCC_SDCC2_BCR] = { 0x24000 },
3195 [GCC_SDCC4_BCR] = { 0x26000 },
3196 [GCC_UFS_PHY_BCR] = { 0x87000 },
3197 [GCC_USB30_PRIM_BCR] = { 0x49000 },
3198 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
3199 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
3200 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
3201 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
3202 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
3203 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
3204 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
3205 [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
3206 [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
3207 [GCC_VIDEO_BCR] = { 0x42000 },
3246 .max_register = 0x1f1030,
3284 qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ in gcc_sm8450_probe()
3285 qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ in gcc_sm8450_probe()
3286 qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ in gcc_sm8450_probe()
3287 qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ in gcc_sm8450_probe()
3288 qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sm8450_probe()
3289 qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ in gcc_sm8450_probe()
3290 qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ in gcc_sm8450_probe()