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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Drealtek,otto-gpio.yaml24 pattern: "^gpio@[0-9a-f]+$"
86 reg = <0x3500 0x1c>;
98 reg = <0x3300 0x1c>, <0x3338 0x8>;
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dg84.c39 return (nvkm_rd32(device, 0x00154c) & 0x1) + 1; in g84_pcie_version()
46 nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0)); in g84_pcie_set_version()
53 nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0); in g84_pcie_set_cap_speed()
59 u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000; in g84_pcie_cur_speed()
61 case 0x30000: in g84_pcie_cur_speed()
63 case 0x20000: in g84_pcie_cur_speed()
65 case 0x10000: in g84_pcie_cur_speed()
74 u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300; in g84_pcie_max_speed()
75 if (reg_v == 0x2200) in g84_pcie_max_speed()
86 mask_value = 0x20; in g84_pcie_set_link_speed()
[all …]
/linux-6.12.1/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux-6.12.1/drivers/mfd/
Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
Darizona-core.c38 int ret = 0; in arizona_clk32k_enable()
48 if (ret != 0) in arizona_clk32k_enable()
51 if (ret != 0) { in arizona_clk32k_enable()
58 if (ret != 0) in arizona_clk32k_enable()
69 if (ret != 0) in arizona_clk32k_enable()
82 WARN_ON(arizona->clk32k_ref <= 0); in arizona_clk32k_disable()
86 if (arizona->clk32k_ref == 0) { in arizona_clk32k_disable()
88 ARIZONA_CLK_32K_ENA, 0); in arizona_clk32k_disable()
103 return 0; in arizona_clk32k_disable()
124 if (ret != 0) { in arizona_underclocked()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_fbc_regs.h9 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
10 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
11 #define FBC_CONTROL _MMIO(0x3208)
21 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
23 #define FBC_COMMAND _MMIO(0x320c)
24 #define FBC_CMD_COMPRESS REG_BIT(0)
25 #define FBC_STATUS _MMIO(0x3210)
29 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
30 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
33 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
[all …]
/linux-6.12.1/drivers/staging/rtl8712/
Dusb_intf.c41 {USB_DEVICE(0x0BDA, 0x8171)},
42 {USB_DEVICE(0x0bda, 0x8173)},
43 {USB_DEVICE(0x0bda, 0x8712)},
44 {USB_DEVICE(0x0bda, 0x8713)},
45 {USB_DEVICE(0x0bda, 0xC512)},
47 {USB_DEVICE(0x07B8, 0x8188)},
49 {USB_DEVICE(0x0B05, 0x1786)},
50 {USB_DEVICE(0x0B05, 0x1791)}, /* 11n mode disable */
52 {USB_DEVICE(0x050D, 0x945A)},
54 {USB_DEVICE(0x050D, 0x11F1)},
[all …]
/linux-6.12.1/drivers/gpu/drm/mediatek/
Dmtk_dp_reg.h9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
[all …]
/linux-6.12.1/drivers/media/dvb-frontends/
Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux-6.12.1/drivers/bus/
Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/linux-6.12.1/drivers/hwmon/
Djc42.c27 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
30 #define JC42_REG_CAP 0x00
31 #define JC42_REG_CONFIG 0x01
32 #define JC42_REG_TEMP_UPPER 0x02
33 #define JC42_REG_TEMP_LOWER 0x03
34 #define JC42_REG_TEMP_CRITICAL 0x04
35 #define JC42_REG_TEMP 0x05
36 #define JC42_REG_MANID 0x06
37 #define JC42_REG_DEVICEID 0x07
38 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgt215.c103 u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; in gt215_link_train_calc()
105 for (i = 0; i < 8; i++) { in gt215_link_train_calc()
106 for (lo = 0; lo < 0x40; lo++) { in gt215_link_train_calc()
107 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
109 if (vals[lo] & (0x101 << i)) in gt215_link_train_calc()
113 if (lo == 0x40) in gt215_link_train_calc()
116 for (hi = lo + 1; hi < 0x40; hi++) { in gt215_link_train_calc()
117 if (!(vals[lo] & 0x80000000)) in gt215_link_train_calc()
119 if (!(vals[hi] & (0x101 << i))) { in gt215_link_train_calc()
126 bins[(median[i] & 0xf0) >> 4]++; in gt215_link_train_calc()
[all …]
/linux-6.12.1/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux-6.12.1/drivers/media/usb/pwc/
Dpwc-ctrl.c41 #define GET_STATUS_B00 0x0B00
42 #define SENSOR_TYPE_FORMATTER1 0x0C00
43 #define GET_STATUS_3000 0x3000
44 #define READ_RAW_Y_MEAN_FORMATTER 0x3100
45 #define SET_POWER_SAVE_MODE_FORMATTER 0x3200
46 #define MIRROR_IMAGE_FORMATTER 0x3300
47 #define LED_FORMATTER 0x3400
48 #define LOWLIGHT 0x3500
49 #define GET_STATUS_3600 0x3600
50 #define SENSOR_TYPE_FORMATTER2 0x3700
[all …]
/linux-6.12.1/sound/soc/sh/rcar/
Dsrc.c51 for ((i) = 0; \
69 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_activation()
76 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_halt()
98 return 0; in rsnd_src_convert_rate()
120 unsigned int rate = 0; in rsnd_src_get_rate()
148 0x01800000, /* 6 - 1/6 */
149 0x01000000, /* 6 - 1/4 */
150 0x00c00000, /* 6 - 1/3 */
151 0x00800000, /* 6 - 1/2 */
152 0x00600000, /* 6 - 2/3 */
[all …]
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mt7629.c12 MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
15 PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
19 PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
23 PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
27 PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
31 PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
32 PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
33 PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
34 PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
35 PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
[all …]
/linux-6.12.1/drivers/net/ethernet/smsc/
Dsmc91x.c15 * nowait = 0 for normal wait states, 1 eliminates additional wait states
52 #define SMC_DEBUG 0
88 # define SMC_NOWAIT 0
137 #define THROTTLE_TX_PKTS 0
149 } while (0)
153 if (SMC_DEBUG > 0) \
157 } while (0)
169 for (i = 0; i < lines ; i ++) { in PRINT_PKT()
172 for (cur = 0; cur < 8; cur++) { in PRINT_PKT()
181 for (i = 0; i < remainder/2 ; i++) { in PRINT_PKT()
[all …]
Dsmc9194.c17 . ifport = 0 for autodetect, 1 for TP, 2 for AUI ( or 10base2 )
110 {.port = 0x200, .irq = 0},
111 {.port = 0x220, .irq = 0},
112 {.port = 0x240, .irq = 0},
113 {.port = 0x260, .irq = 0},
114 {.port = 0x280, .irq = 0},
115 {.port = 0x2A0, .irq = 0},
116 {.port = 0x2C0, .irq = 0},
117 {.port = 0x2E0, .irq = 0},
118 {.port = 0x300, .irq = 0},
[all …]
/linux-6.12.1/drivers/soc/fsl/qbman/
Dbman.c40 #define BM_REG_RCR_PI_CINH 0x3000
41 #define BM_REG_RCR_CI_CINH 0x3100
42 #define BM_REG_RCR_ITR 0x3200
43 #define BM_REG_CFG 0x3300
44 #define BM_REG_SCN(n) (0x3400 + ((n) << 6))
45 #define BM_REG_ISR 0x3e00
46 #define BM_REG_IER 0x3e40
47 #define BM_REG_ISDR 0x3e80
48 #define BM_REG_IIR 0x3ec0
51 #define BM_CL_CR 0x0000
[all …]
Dqman.c40 #define QMAN_ITP_MAX 0xFFF
48 #define QM_REG_EQCR_PI_CINH 0x3000
49 #define QM_REG_EQCR_CI_CINH 0x3040
50 #define QM_REG_EQCR_ITR 0x3080
51 #define QM_REG_DQRR_PI_CINH 0x3100
52 #define QM_REG_DQRR_CI_CINH 0x3140
53 #define QM_REG_DQRR_ITR 0x3180
54 #define QM_REG_DQRR_DCAP 0x31C0
55 #define QM_REG_DQRR_SDQCR 0x3200
56 #define QM_REG_DQRR_VDQCR 0x3240
[all …]
/linux-6.12.1/drivers/media/i2c/
Dhi846.c22 #define HI846_REG_FLL 0x0006
23 #define HI846_FLL_MAX 0xffff
26 #define HI846_REG_LLP 0x0008
29 #define HI846_REG_BINNING_MODE 0x000c
31 #define HI846_REG_IMAGE_ORIENTATION 0x000e
33 #define HI846_REG_UNKNOWN_0022 0x0022
35 #define HI846_REG_Y_ADDR_START_VACT_H 0x0026
36 #define HI846_REG_Y_ADDR_START_VACT_L 0x0027
37 #define HI846_REG_UNKNOWN_0028 0x0028
39 #define HI846_REG_Y_ADDR_END_VACT_H 0x002c
[all …]
Dimx296.c30 #define IMX296_REG_ADDR_MASK 0xffff
32 #define IMX296_CTRL00 IMX296_REG_8BIT(0x3000)
33 #define IMX296_CTRL00_STANDBY BIT(0)
34 #define IMX296_CTRL08 IMX296_REG_8BIT(0x3008)
35 #define IMX296_CTRL08_REGHOLD BIT(0)
36 #define IMX296_CTRL0A IMX296_REG_8BIT(0x300a)
37 #define IMX296_CTRL0A_XMSTA BIT(0)
38 #define IMX296_CTRL0B IMX296_REG_8BIT(0x300b)
39 #define IMX296_CTRL0B_TRIGEN BIT(0)
40 #define IMX296_CTRL0D IMX296_REG_8BIT(0x300d)
[all …]
Dimx334.c20 #define IMX334_REG_MODE_SELECT 0x3000
21 #define IMX334_MODE_STANDBY 0x01
22 #define IMX334_MODE_STREAMING 0x00
25 #define IMX334_REG_LPFR 0x3030
28 #define IMX334_REG_ID 0x3044
29 #define IMX334_ID 0x1e
32 #define IMX334_REG_SHUTTER 0x3058
36 #define IMX334_EXPOSURE_DEFAULT 0x0648
39 #define IMX334_REG_AGAIN 0x30e8
40 #define IMX334_AGAIN_MIN 0
[all …]
/linux-6.12.1/sound/soc/codecs/
Drt1305.c31 #define RT1305_PR_RANGE_BASE (0xff + 1)
32 #define RT1305_PR_SPACING 0x100
34 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
41 .range_max = RT1305_PR_BASE + 0xff,
43 .selector_mask = 0xff,
44 .selector_shift = 0x0,
46 .window_len = 0x1,
53 { RT1305_PR_BASE + 0xcf, 0x5548 },
54 { RT1305_PR_BASE + 0x5d, 0x0442 },
55 { RT1305_PR_BASE + 0xc1, 0x0320 },
[all …]
/linux-6.12.1/drivers/scsi/
Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]

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