Lines Matching +full:0 +full:x3300
30 #define IMX296_REG_ADDR_MASK 0xffff
32 #define IMX296_CTRL00 IMX296_REG_8BIT(0x3000)
33 #define IMX296_CTRL00_STANDBY BIT(0)
34 #define IMX296_CTRL08 IMX296_REG_8BIT(0x3008)
35 #define IMX296_CTRL08_REGHOLD BIT(0)
36 #define IMX296_CTRL0A IMX296_REG_8BIT(0x300a)
37 #define IMX296_CTRL0A_XMSTA BIT(0)
38 #define IMX296_CTRL0B IMX296_REG_8BIT(0x300b)
39 #define IMX296_CTRL0B_TRIGEN BIT(0)
40 #define IMX296_CTRL0D IMX296_REG_8BIT(0x300d)
41 #define IMX296_CTRL0D_WINMODE_ALL (0 << 0)
42 #define IMX296_CTRL0D_WINMODE_FD_BINNING (2 << 0)
45 #define IMX296_CTRL0E IMX296_REG_8BIT(0x300e)
46 #define IMX296_CTRL0E_VREVERSE BIT(0)
48 #define IMX296_VMAX IMX296_REG_24BIT(0x3010)
49 #define IMX296_HMAX IMX296_REG_16BIT(0x3014)
50 #define IMX296_TMDCTRL IMX296_REG_8BIT(0x301d)
51 #define IMX296_TMDCTRL_LATCH BIT(0)
52 #define IMX296_TMDOUT IMX296_REG_16BIT(0x301e)
53 #define IMX296_TMDOUT_MASK 0x3ff
54 #define IMX296_WDSEL IMX296_REG_8BIT(0x3021)
55 #define IMX296_WDSEL_NORMAL (0 << 0)
56 #define IMX296_WDSEL_MULTI_2 (1 << 0)
57 #define IMX296_WDSEL_MULTI_4 (3 << 0)
58 #define IMX296_BLKLEVELAUTO IMX296_REG_8BIT(0x3022)
59 #define IMX296_BLKLEVELAUTO_ON 0x01
60 #define IMX296_BLKLEVELAUTO_OFF 0xf0
61 #define IMX296_SST IMX296_REG_8BIT(0x3024)
62 #define IMX296_SST_EN BIT(0)
63 #define IMX296_CTRLTOUT IMX296_REG_8BIT(0x3026)
64 #define IMX296_CTRLTOUT_TOUT1SEL_LOW (0 << 0)
65 #define IMX296_CTRLTOUT_TOUT1SEL_PULSE (3 << 0)
66 #define IMX296_CTRLTOUT_TOUT2SEL_LOW (0 << 2)
68 #define IMX296_CTRLTRIG IMX296_REG_8BIT(0x3029)
69 #define IMX296_CTRLTRIG_TOUT1_SEL_LOW (0 << 0)
70 #define IMX296_CTRLTRIG_TOUT1_SEL_PULSE1 (1 << 0)
71 #define IMX296_CTRLTRIG_TOUT2_SEL_LOW (0 << 4)
73 #define IMX296_SYNCSEL IMX296_REG_8BIT(0x3036)
74 #define IMX296_SYNCSEL_NORMAL 0xc0
75 #define IMX296_SYNCSEL_HIZ 0xf0
76 #define IMX296_PULSE1 IMX296_REG_8BIT(0x306d)
77 #define IMX296_PULSE1_EN_NOR BIT(0)
79 #define IMX296_PULSE1_POL_HIGH (0 << 2)
81 #define IMX296_PULSE1_UP IMX296_REG_24BIT(0x3070)
82 #define IMX296_PULSE1_DN IMX296_REG_24BIT(0x3074)
83 #define IMX296_PULSE2 IMX296_REG_8BIT(0x3079)
84 #define IMX296_PULSE2_EN_NOR BIT(0)
86 #define IMX296_PULSE2_POL_HIGH (0 << 2)
88 #define IMX296_PULSE2_UP IMX296_REG_24BIT(0x307c)
89 #define IMX296_PULSE2_DN IMX296_REG_24BIT(0x3080)
90 #define IMX296_INCKSEL(n) IMX296_REG_8BIT(0x3089 + (n))
91 #define IMX296_SHS1 IMX296_REG_24BIT(0x308d)
92 #define IMX296_SHS2 IMX296_REG_24BIT(0x3090)
93 #define IMX296_SHS3 IMX296_REG_24BIT(0x3094)
94 #define IMX296_SHS4 IMX296_REG_24BIT(0x3098)
95 #define IMX296_VBLANKLP IMX296_REG_8BIT(0x309c)
96 #define IMX296_VBLANKLP_NORMAL 0x04
97 #define IMX296_VBLANKLP_LOW_POWER 0x2c
98 #define IMX296_EXP_CNT IMX296_REG_8BIT(0x30a3)
99 #define IMX296_EXP_CNT_RESET BIT(0)
100 #define IMX296_EXP_MAX IMX296_REG_16BIT(0x30a6)
101 #define IMX296_VINT IMX296_REG_8BIT(0x30aa)
102 #define IMX296_VINT_EN BIT(0)
103 #define IMX296_LOWLAGTRG IMX296_REG_8BIT(0x30ae)
104 #define IMX296_LOWLAGTRG_FAST BIT(0)
105 #define IMX296_I2CCTRL IMX296_REG_8BIT(0x30ef)
106 #define IMX296_I2CCTRL_I2CACKEN BIT(0)
108 #define IMX296_SENSOR_INFO IMX296_REG_16BIT(0x3148)
110 #define IMX296_SENSOR_INFO_IMX296LQ 0x4a00
111 #define IMX296_SENSOR_INFO_IMX296LL 0xca00
112 #define IMX296_S_SHSA IMX296_REG_16BIT(0x31ca)
113 #define IMX296_S_SHSB IMX296_REG_16BIT(0x31d2)
115 * Registers 0x31c8 to 0x31cd, 0x31d0 to 0x31d5, 0x31e2, 0x31e3, 0x31ea and
116 * 0x31eb are related to exposure mode but otherwise not documented.
119 #define IMX296_GAINCTRL IMX296_REG_8BIT(0x3200)
120 #define IMX296_GAINCTRL_WD_GAIN_MODE_NORMAL 0x01
121 #define IMX296_GAINCTRL_WD_GAIN_MODE_MULTI 0x41
122 #define IMX296_GAIN IMX296_REG_16BIT(0x3204)
123 #define IMX296_GAIN_MIN 0
125 #define IMX296_GAIN1 IMX296_REG_16BIT(0x3208)
126 #define IMX296_GAIN2 IMX296_REG_16BIT(0x320c)
127 #define IMX296_GAIN3 IMX296_REG_16BIT(0x3210)
128 #define IMX296_GAINDLY IMX296_REG_8BIT(0x3212)
129 #define IMX296_GAINDLY_NONE 0x08
130 #define IMX296_GAINDLY_1FRAME 0x09
131 #define IMX296_PGCTRL IMX296_REG_8BIT(0x3238)
132 #define IMX296_PGCTRL_REGEN BIT(0)
136 #define IMX296_PGHPOS IMX296_REG_16BIT(0x3239)
137 #define IMX296_PGVPOS IMX296_REG_16BIT(0x323c)
138 #define IMX296_PGHPSTEP IMX296_REG_8BIT(0x323e)
139 #define IMX296_PGVPSTEP IMX296_REG_8BIT(0x323f)
140 #define IMX296_PGHPNUM IMX296_REG_8BIT(0x3240)
141 #define IMX296_PGVPNUM IMX296_REG_8BIT(0x3241)
142 #define IMX296_PGDATA1 IMX296_REG_16BIT(0x3244)
143 #define IMX296_PGDATA2 IMX296_REG_16BIT(0x3246)
144 #define IMX296_PGHGSTEP IMX296_REG_8BIT(0x3249)
145 #define IMX296_BLKLEVEL IMX296_REG_16BIT(0x3254)
147 #define IMX296_FID0_ROI IMX296_REG_8BIT(0x3300)
148 #define IMX296_FID0_ROIH1ON BIT(0)
150 #define IMX296_FID0_ROIPH1 IMX296_REG_16BIT(0x3310)
151 #define IMX296_FID0_ROIPV1 IMX296_REG_16BIT(0x3312)
152 #define IMX296_FID0_ROIWH1 IMX296_REG_16BIT(0x3314)
154 #define IMX296_FID0_ROIWV1 IMX296_REG_16BIT(0x3316)
157 #define IMX296_CM_HSST_STARTTMG IMX296_REG_16BIT(0x4018)
158 #define IMX296_CM_HSST_ENDTMG IMX296_REG_16BIT(0x401a)
159 #define IMX296_DA_HSST_STARTTMG IMX296_REG_16BIT(0x404d)
160 #define IMX296_DA_HSST_ENDTMG IMX296_REG_16BIT(0x4050)
161 #define IMX296_LM_HSST_STARTTMG IMX296_REG_16BIT(0x4094)
162 #define IMX296_LM_HSST_ENDTMG IMX296_REG_16BIT(0x4096)
163 #define IMX296_SST_SIEASTA1_SET IMX296_REG_8BIT(0x40c9)
164 #define IMX296_SST_SIEASTA1PRE_1U IMX296_REG_16BIT(0x40cc)
165 #define IMX296_SST_SIEASTA1PRE_1D IMX296_REG_16BIT(0x40ce)
166 #define IMX296_SST_SIEASTA1PRE_2U IMX296_REG_16BIT(0x40d0)
167 #define IMX296_SST_SIEASTA1PRE_2D IMX296_REG_16BIT(0x40d2)
168 #define IMX296_HSST IMX296_REG_8BIT(0x40dc)
171 #define IMX296_CKREQSEL IMX296_REG_8BIT(0x4101)
173 #define IMX296_GTTABLENUM IMX296_REG_8BIT(0x4114)
174 #define IMX296_CTRL418C IMX296_REG_8BIT(0x418c)
183 { 37125000, { 0x80, 0x0b, 0x80, 0x08 }, 116 },
184 { 54000000, { 0xb0, 0x0f, 0xb0, 0x0c }, 168 },
185 { 74250000, { 0x80, 0x0f, 0x80, 0x0c }, 232 },
219 u8 data[3] = { 0, 0, 0 }; in imx296_read()
224 if (ret < 0) in imx296_read()
227 return (data[2] << 16) | (data[1] << 8) | data[0]; in imx296_read()
232 u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 }; in imx296_write()
240 if (ret < 0) { in imx296_write()
241 dev_err(sensor->dev, "%u-bit write to 0x%04x failed: %d\n", in imx296_write()
257 if (ret < 0) in imx296_power_on()
262 ret = gpiod_direction_output(sensor->reset, 0); in imx296_power_on()
263 if (ret < 0) in imx296_power_on()
269 if (ret < 0) in imx296_power_on()
281 return 0; in imx296_power_on()
320 int ret = 0; in imx296_s_ctrl()
323 return 0; in imx296_s_ctrl()
326 format = v4l2_subdev_state_get_format(state, 0); in imx296_s_ctrl()
353 imx296_write(sensor, IMX296_PGDATA1, 0x300, &ret); in imx296_s_ctrl()
354 imx296_write(sensor, IMX296_PGDATA2, 0x100, &ret); in imx296_s_ctrl()
355 imx296_write(sensor, IMX296_PGHGSTEP, 0, &ret); in imx296_s_ctrl()
356 imx296_write(sensor, IMX296_BLKLEVEL, 0, &ret); in imx296_s_ctrl()
366 imx296_write(sensor, IMX296_BLKLEVEL, 0x3c, &ret); in imx296_s_ctrl()
393 if (ret < 0) in imx296_ctrls_init()
434 0, 0, imx296_test_pattern_menu); in imx296_ctrls_init()
448 return 0; in imx296_ctrls_init()
464 { IMX296_REG_8BIT(0x3005), 0xf0 },
465 { IMX296_REG_8BIT(0x309e), 0x04 },
466 { IMX296_REG_8BIT(0x30a0), 0x04 },
467 { IMX296_REG_8BIT(0x30a1), 0x3c },
468 { IMX296_REG_8BIT(0x30a4), 0x5f },
469 { IMX296_REG_8BIT(0x30a8), 0x91 },
470 { IMX296_REG_8BIT(0x30ac), 0x28 },
471 { IMX296_REG_8BIT(0x30af), 0x09 },
472 { IMX296_REG_8BIT(0x30df), 0x00 },
473 { IMX296_REG_8BIT(0x3165), 0x00 },
474 { IMX296_REG_8BIT(0x3169), 0x10 },
475 { IMX296_REG_8BIT(0x316a), 0x02 },
476 { IMX296_REG_8BIT(0x31c8), 0xf3 }, /* Exposure-related */
477 { IMX296_REG_8BIT(0x31d0), 0xf4 }, /* Exposure-related */
478 { IMX296_REG_8BIT(0x321a), 0x00 },
479 { IMX296_REG_8BIT(0x3226), 0x02 },
480 { IMX296_REG_8BIT(0x3256), 0x01 },
481 { IMX296_REG_8BIT(0x3541), 0x72 },
482 { IMX296_REG_8BIT(0x3516), 0x77 },
483 { IMX296_REG_8BIT(0x350b), 0x7f },
484 { IMX296_REG_8BIT(0x3758), 0xa3 },
485 { IMX296_REG_8BIT(0x3759), 0x00 },
486 { IMX296_REG_8BIT(0x375a), 0x85 },
487 { IMX296_REG_8BIT(0x375b), 0x00 },
488 { IMX296_REG_8BIT(0x3832), 0xf5 },
489 { IMX296_REG_8BIT(0x3833), 0x00 },
490 { IMX296_REG_8BIT(0x38a2), 0xf6 },
491 { IMX296_REG_8BIT(0x38a3), 0x00 },
492 { IMX296_REG_8BIT(0x3a00), 0x80 },
493 { IMX296_REG_8BIT(0x3d48), 0xa3 },
494 { IMX296_REG_8BIT(0x3d49), 0x00 },
495 { IMX296_REG_8BIT(0x3d4a), 0x85 },
496 { IMX296_REG_8BIT(0x3d4b), 0x00 },
497 { IMX296_REG_8BIT(0x400e), 0x58 },
498 { IMX296_REG_8BIT(0x4014), 0x1c },
499 { IMX296_REG_8BIT(0x4041), 0x2a },
500 { IMX296_REG_8BIT(0x40a2), 0x06 },
501 { IMX296_REG_8BIT(0x40c1), 0xf6 },
502 { IMX296_REG_8BIT(0x40c7), 0x0f },
503 { IMX296_REG_8BIT(0x40c8), 0x00 },
504 { IMX296_REG_8BIT(0x4174), 0x00 },
512 int ret = 0; in imx296_setup()
514 format = v4l2_subdev_state_get_format(state, 0); in imx296_setup()
515 crop = v4l2_subdev_state_get_crop(state, 0); in imx296_setup()
517 for (i = 0; i < ARRAY_SIZE(imx296_init_table); ++i) in imx296_setup()
530 imx296_write(sensor, IMX296_FID0_ROI, 0, &ret); in imx296_setup()
535 IMX296_CTRL0D_HADD_ON_BINNING : 0) | in imx296_setup()
537 IMX296_CTRL0D_WINMODE_FD_BINNING : 0), in imx296_setup()
551 * - two lines of embedded data (DT 0x12) in imx296_setup()
552 * - six null lines (DT 0x10) in imx296_setup()
553 * - four lines of vertical effective optical black (DT 0x37) in imx296_setup()
554 * - 8 to 1088 lines of active image data (RAW10, DT 0x2b) in imx296_setup()
562 for (i = 0; i < ARRAY_SIZE(sensor->clk_params->incksel); ++i) in imx296_setup()
565 imx296_write(sensor, IMX296_GTTABLENUM, 0xc5, &ret); in imx296_setup()
570 imx296_write(sensor, IMX296_BLKLEVEL, 0x03c, &ret); in imx296_setup()
577 int ret = 0; in imx296_stream_on()
579 imx296_write(sensor, IMX296_CTRL00, 0, &ret); in imx296_stream_on()
581 imx296_write(sensor, IMX296_CTRL0A, 0, &ret); in imx296_stream_on()
588 int ret = 0; in imx296_stream_off()
614 if (ret < 0) in imx296_s_stream()
618 if (ret < 0) in imx296_s_stream()
622 if (ret < 0) in imx296_s_stream()
650 if (code->index != 0) in imx296_enum_mbus_code()
656 return 0; in imx296_enum_mbus_code()
675 return 0; in imx296_enum_frame_size()
726 return 0; in imx296_set_format()
741 sel->r.left = 0; in imx296_get_selection()
742 sel->r.top = 0; in imx296_get_selection()
751 return 0; in imx296_get_selection()
769 rect.left = clamp(ALIGN(sel->r.left, 4), 0, in imx296_set_selection()
771 rect.top = clamp(ALIGN(sel->r.top, 4), 0, in imx296_set_selection()
798 return 0; in imx296_set_selection()
819 return 0; in imx296_init_state()
853 if (ret < 0) in imx296_subdev_init()
860 if (ret < 0) { in imx296_subdev_init()
899 return 0; in imx296_runtime_suspend()
916 if (ret < 0) in imx296_read_temperature()
920 if (tmdout < 0) in imx296_read_temperature()
928 return imx296_write(sensor, IMX296_TMDCTRL, 0, NULL); in imx296_read_temperature()
934 int temp = 0; in imx296_identify_model()
940 "sensor model auto-detection disabled, forcing 0x%04x\n", in imx296_identify_model()
943 return 0; in imx296_identify_model()
950 ret = imx296_write(sensor, IMX296_CTRL00, 0, NULL); in imx296_identify_model()
951 if (ret < 0) { in imx296_identify_model()
958 if (ret < 0) { in imx296_identify_model()
964 model = (ret >> 6) & 0x1ff; in imx296_identify_model()
976 dev_err(sensor->dev, "invalid device model 0x%04x\n", ret); in imx296_identify_model()
982 if (ret < 0) in imx296_identify_model()
1000 .range_min = IMX296_SENSOR_INFO & 0xffff,
1001 .range_max = (IMX296_SENSOR_INFO & 0xffff) + 1,
1029 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i) in imx296_probe()
1051 for (i = 0; i < ARRAY_SIZE(imx296_clk_params); ++i) { in imx296_probe()
1073 if (ret < 0) in imx296_probe()
1077 if (ret < 0) in imx296_probe()
1082 if (ret < 0) in imx296_probe()
1095 if (ret < 0) in imx296_probe()
1107 return 0; in imx296_probe()