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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dqoriq-sata2-0.dtsi2 * QorIQ SATAv2 device tree stub [ controller @ offset 0x220000 ]
37 reg = <0x220000 0x1000>;
38 interrupts = <68 0x2 0 0>;
/linux-6.12.1/Documentation/devicetree/bindings/net/
Ddavinci_emac.txt32 reg = <0x220000 0x4000>;
33 ti,davinci-ctrl-reg-offset = <0x3000>;
34 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
35 ti,davinci-ctrl-ram-offset = <0>;
36 ti,davinci-ctrl-ram-size = <0x2000>;
Dmarvell,pp2.yaml32 const: 0
59 '^(ethernet-)?port@[0-2]$':
92 "hifX", with X in [0..8], and "link". The names "tx-cpu0",
165 '^(ethernet-)?port@[0-2]$':
187 '^(ethernet-)?port@[0-1]$':
204 #size-cells = <0>;
206 reg = <0xf0000 0xa000>,
207 <0xc0000 0x3060>,
208 <0xc4000 0x100>,
209 <0xc5000 0x100>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/linux-6.12.1/drivers/media/pci/intel/ipu6/
Dipu6-platform-isys-csi2-reg.h9 #define CSI_REG_BASE 0x220000
10 #define CSI_REG_PORT_BASE(id) (CSI_REG_BASE + (id) * 0x1000)
13 #define CSI_REG_PORT_GPREG_SRST 0x0
14 #define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST 0x4
15 #define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL 0x8
24 #define CSI_PORT_REG_BASE_IRQ_CSI 0x80
25 #define CSI_PORT_REG_BASE_IRQ_CSI_SYNC 0xA0
26 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7 0xC0
27 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15 0xE0
29 #define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET 0x0
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2g-netcp.dtsi13 power-domains = <&k2g_pds 0x0018>;
14 clocks = <&k2g_clks 0x0018 0>;
17 queue-range = <0 0x80>;
18 linkram0 = <0x4020000 0x7ff>;
26 managed-queues = <0 0x80>;
27 reg = <0x4100000 0x800>,
28 <0x4040000 0x100>,
29 <0x4080000 0x800>,
30 <0x40c0000 0x800>;
38 qpend-0 {
[all …]
Dkeystone-k2e-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0 0x10000>;
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
Dkeystone-k2l-netcp.dtsi15 queue-range = <0 0x2000>;
16 linkram0 = <0x100000 0x4000>;
17 linkram1 = <0x70000000 0x10000>; /* 1MB OSR mem */
24 managed-queues = <0 0x2000>;
25 reg = <0x2a40000 0x20000>,
26 <0x2a06000 0x400>,
27 <0x2a02000 0x1000>,
28 <0x2a03000 0x1000>,
29 <0x23a80000 0x20000>,
30 <0x2a80000 0x20000>;
[all …]
/linux-6.12.1/drivers/net/ethernet/cavium/thunder/
Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/sn0/
Dhubmd.h29 #define MD_BASE 0x200000
30 #define MD_BASE_PERF 0x210000
31 #define MD_BASE_JUNK 0x220000
33 #define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34 #define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35 #define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36 #define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37 #define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39 #define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi41 reg = <0x0 0x4000000 0x0 0x200000>;
46 reg = <0 0x4400000 0 0x1000000>;
62 ranges = <0x0 0x0 0xf0000000 0x1000000>;
66 reg = <0x100000 0x100000>;
90 reg = <0x210000 0x10000>,
91 <0x220000 0x20000>,
92 <0x240000 0x20000>,
93 <0x260000 0x20000>;
98 reg = <0x280000 0x1000>;
105 reg = <0x290000 0x1000>;
[all …]
Darmada-cp11x.dtsi29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
62 #size-cells = <0>;
64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
74 CP11X_LABEL(eth0): ethernet-port@0 {
88 reg = <0>;
89 port-id = <0>; /* For backward compatibility. */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/apm/
Dapm-shadowcat.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
26 clocks = <&pmd0clk 0>;
31 reg = <0x0 0x001>;
33 cpu-release-addr = <0x1 0x0000fff8>;
36 clocks = <&pmd0clk 0>;
41 reg = <0x0 0x100>;
43 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/davinci/
Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/linux-6.12.1/drivers/net/wireless/intel/ipw2x00/
Dipw2100.h41 #define IPW_DL_UNINIT 0x80000000
42 #define IPW_DL_NONE 0x00000000
43 #define IPW_DL_ALL 0x7FFFFFFF
71 #define IPW_DL_ERROR (1<<0)
121 IPW_HW_STATE_ENABLED = 0
159 #define IPW_BD_STATUS_TX_FRAME_802_3 0x00
160 #define IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT 0x01
161 #define IPW_BD_STATUS_TX_FRAME_COMMAND 0x02
162 #define IPW_BD_STATUS_TX_FRAME_802_11 0x04
163 #define IPW_BD_STATUS_TX_INTERRUPT_ENABLE 0x08
[all …]
/linux-6.12.1/drivers/phy/microchip/
Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsdm630.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
55 reg = <0x0 0x100>;
75 reg = <0x0 0x101>;
90 reg = <0x0 0x102>;
105 reg = <0x0 0x103>;
117 CPU4: cpu@0 {
120 reg = <0x0 0x0>;
140 reg = <0x0 0x1>;
[all …]
Dmsm8998.dtsi16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
/linux-6.12.1/sound/soc/codecs/
Dcs47l85.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]
Dcs47l90.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]
/linux-6.12.1/drivers/mfd/
Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
Dcs47l85-tables.c18 { 0x80, 0x0003 },
19 { 0x213, 0x03E4 },
20 { 0x177, 0x0281 },
21 { 0x197, 0x0281 },
22 { 0x1B7, 0x0281 },
23 { 0x4B1, 0x010A },
24 { 0x4CF, 0x0933 },
25 { 0x36C, 0x011B },
26 { 0x4B8, 0x1120 },
27 { 0x4A0, 0x3280 },
[all …]