Lines Matching +full:0 +full:x220000
41 #define IPW_DL_UNINIT 0x80000000
42 #define IPW_DL_NONE 0x00000000
43 #define IPW_DL_ALL 0x7FFFFFFF
71 #define IPW_DL_ERROR (1<<0)
121 IPW_HW_STATE_ENABLED = 0
159 #define IPW_BD_STATUS_TX_FRAME_802_3 0x00
160 #define IPW_BD_STATUS_TX_FRAME_NOT_LAST_FRAGMENT 0x01
161 #define IPW_BD_STATUS_TX_FRAME_COMMAND 0x02
162 #define IPW_BD_STATUS_TX_FRAME_802_11 0x04
163 #define IPW_BD_STATUS_TX_INTERRUPT_ENABLE 0x08
195 #define STATUS_TYPE_MASK 0x0000000f
196 #define COMMAND_STATUS_VAL 0
208 #define IPW_STATUS_FLAG_DECRYPTED (1<<0)
228 #define IPW_WPA_CAPABILITIES 0x1
229 #define IPW_WPA_LISTENINTERVAL 0x2
230 #define IPW_WPA_AP_ADDRESS 0x4
280 u8 wep_index; // 0 no key, 1-4 key index, 0xff immediate key
281 u8 key_size; // 0 no imm key, 0x5 64bit encr, 0xd 128bit encr, 0x10 128bit encr and 128bit IV
307 COMMAND = 0xCAFE,
370 #define IPW_NONE_CIPHER (1<<0)
377 #define IPW_AUTH_OPEN 0
380 #define IPW_AUTH_LEAP_CISCO_ID 0x80
389 (x)->value = (x)->hi = 0; \
390 (x)->lo = 0x7fffffff; \
391 } while (0)
396 } while (0)
398 while (0)
400 while (0)
407 IPW2100_PM_DISABLED = 0,
411 PM_STATE_SIZE = 0,
415 #define STATUS_POWERED (1<<0)
438 #define IPW_STATE_INITIALIZED (1<<0)
451 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
464 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
502 u8 *snapshot[0x30];
641 #define IPW_CFG_MONITOR 0x00004
642 #define IPW_CFG_PREAMBLE_AUTO 0x00010
643 #define IPW_CFG_IBSS_AUTO_START 0x00020
644 #define IPW_CFG_LOOPBACK 0x00100
645 #define IPW_CFG_ANSWER_BCSSID_PROBE 0x00800
646 #define IPW_CFG_BT_SIDEBAND_SIGNAL 0x02000
647 #define IPW_CFG_802_1x_ENABLE 0x04000
648 #define IPW_CFG_BSS_MASK 0x08000
649 #define IPW_CFG_IBSS_MASK 0x10000
651 #define IPW_SCAN_NOASSOCIATE (1<<0)
656 #define IPW_NIC_FATAL_ERROR 0x2A7F0
657 #define IPW_ERROR_ADDR(x) (x & 0x3FFFF)
658 #define IPW_ERROR_CODE(x) ((x & 0xFF000000) >> 24)
659 #define IPW2100_ERR_C3_CORRUPTION (0x10 << 24)
660 #define IPW2100_ERR_MSG_TIMEOUT (0x11 << 24)
661 #define IPW2100_ERR_FW_LOAD (0x12 << 24)
663 #define IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND 0x200
664 #define IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x0D80
666 #define IPW_MEM_HOST_SHARED_RX_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x4…
667 #define IPW_MEM_HOST_SHARED_RX_STATUS_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x4…
668 #define IPW_MEM_HOST_SHARED_RX_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x4…
669 #define IPW_MEM_HOST_SHARED_RX_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0xa…
671 #define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_BASE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x00)
672 #define IPW_MEM_HOST_SHARED_TX_QUEUE_BD_SIZE (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x04)
673 #define IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x80)
676 (IPW_MEM_SRAM_HOST_INTERRUPT_AREA_LOWER_BOUND + 0x20)
681 #define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x180)
682 #define IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2 (IPW_MEM_SRAM_HOST_SHARED_LOWER_BOUND + 0x184)
684 #define IPW2100_INTA_TX_TRANSFER (0x00000001) // Bit 0 (LSB)
685 #define IPW2100_INTA_RX_TRANSFER (0x00000002) // Bit 1
686 #define IPW2100_INTA_TX_COMPLETE (0x00000004) // Bit 2
687 #define IPW2100_INTA_EVENT_INTERRUPT (0x00000008) // Bit 3
688 #define IPW2100_INTA_STATUS_CHANGE (0x00000010) // Bit 4
689 #define IPW2100_INTA_BEACON_PERIOD_EXPIRED (0x00000020) // Bit 5
690 #define IPW2100_INTA_SLAVE_MODE_HOST_COMMAND_DONE (0x00010000) // Bit 16
691 #define IPW2100_INTA_FW_INIT_DONE (0x01000000) // Bit 24
692 #define IPW2100_INTA_FW_CALIBRATION_CALC (0x02000000) // Bit 25
693 #define IPW2100_INTA_FATAL_ERROR (0x40000000) // Bit 30
694 #define IPW2100_INTA_PARITY_ERROR (0x80000000) // Bit 31 (MSB)
696 #define IPW_AUX_HOST_RESET_REG_PRINCETON_RESET (0x00000001)
697 #define IPW_AUX_HOST_RESET_REG_FORCE_NMI (0x00000002)
698 #define IPW_AUX_HOST_RESET_REG_PCI_HOST_CLUSTER_FATAL_NMI (0x00000004)
699 #define IPW_AUX_HOST_RESET_REG_CORE_FATAL_NMI (0x00000008)
700 #define IPW_AUX_HOST_RESET_REG_SW_RESET (0x00000080)
701 #define IPW_AUX_HOST_RESET_REG_MASTER_DISABLED (0x00000100)
702 #define IPW_AUX_HOST_RESET_REG_STOP_MASTER (0x00000200)
704 #define IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY (0x00000001) // Bit 0 (LSB)
705 #define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY (0x00000002) // Bit 1
706 #define IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE (0x00000004) // Bit 2
707 #define IPW_AUX_HOST_GP_CNTRL_BITS_SYS_CONFIG (0x000007c0) // Bits 6-10
708 #define IPW_AUX_HOST_GP_CNTRL_BIT_BUS_TYPE (0x00000200) // Bit 9
709 #define IPW_AUX_HOST_GP_CNTRL_BIT_BAR0_BLOCK_SIZE (0x00000400) // Bit 10
710 #define IPW_AUX_HOST_GP_CNTRL_BIT_USB_MODE (0x20000000) // Bit 29
711 #define IPW_AUX_HOST_GP_CNTRL_BIT_HOST_FORCES_SYS_CLK (0x40000000) // Bit 30
712 #define IPW_AUX_HOST_GP_CNTRL_BIT_FW_FORCES_SYS_CLK (0x80000000) // Bit 31 (MSB)
714 #define IPW_BIT_GPIO_GPIO1_MASK 0x0000000C
715 #define IPW_BIT_GPIO_GPIO3_MASK 0x000000C0
716 #define IPW_BIT_GPIO_GPIO1_ENABLE 0x00000008
717 #define IPW_BIT_GPIO_RF_KILL 0x00010000
719 #define IPW_BIT_GPIO_LED_OFF 0x00002000 // Bit 13 = 1
721 #define IPW_REG_DOMAIN_0_OFFSET 0x0000
724 #define IPW_REG_INTA IPW_REG_DOMAIN_0_OFFSET + 0x0008
725 #define IPW_REG_INTA_MASK IPW_REG_DOMAIN_0_OFFSET + 0x000C
726 #define IPW_REG_INDIRECT_ACCESS_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0010
727 #define IPW_REG_INDIRECT_ACCESS_DATA IPW_REG_DOMAIN_0_OFFSET + 0x0014
728 #define IPW_REG_AUTOINCREMENT_ADDRESS IPW_REG_DOMAIN_0_OFFSET + 0x0018
729 #define IPW_REG_AUTOINCREMENT_DATA IPW_REG_DOMAIN_0_OFFSET + 0x001C
730 #define IPW_REG_RESET_REG IPW_REG_DOMAIN_0_OFFSET + 0x0020
731 #define IPW_REG_GP_CNTRL IPW_REG_DOMAIN_0_OFFSET + 0x0024
732 #define IPW_REG_GPIO IPW_REG_DOMAIN_0_OFFSET + 0x0030
733 #define IPW_REG_FW_TYPE IPW_REG_DOMAIN_1_OFFSET + 0x0188
734 #define IPW_REG_FW_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x018C
735 #define IPW_REG_FW_COMPATIBILITY_VERSION IPW_REG_DOMAIN_1_OFFSET + 0x0190
737 #define IPW_REG_INDIRECT_ADDR_MASK 0x00FFFFFC
739 #define IPW_INTERRUPT_MASK 0xC1010013
741 #define IPW2100_CONTROL_REG 0x220000
742 #define IPW2100_CONTROL_PHY_OFF 0x8
744 #define IPW2100_COMMAND 0x00300004
745 #define IPW2100_COMMAND_PHY_ON 0x0
746 #define IPW2100_COMMAND_PHY_OFF 0x1
748 /* in DEBUG_AREA, values of memory always 0xd55555d5 */
749 #define IPW_REG_DOA_DEBUG_AREA_START IPW_REG_DOMAIN_0_OFFSET + 0x0090
750 #define IPW_REG_DOA_DEBUG_AREA_END IPW_REG_DOMAIN_0_OFFSET + 0x00FF
751 #define IPW_DATA_DOA_DEBUG_VALUE 0xd55555d5
753 #define IPW_INTERNAL_REGISTER_HALT_AND_RESET 0x003000e0
762 #define IPW_CACHE_LINE_LENGTH_DEFAULT 0x80
795 /* Bit 0-7 are for 802.11b tx rates - . Bit 5-7 are reserved */
796 #define TX_RATE_1_MBIT 0x0001
797 #define TX_RATE_2_MBIT 0x0002
798 #define TX_RATE_5_5_MBIT 0x0004
799 #define TX_RATE_11_MBIT 0x0008
800 #define TX_RATE_MASK 0x000F
801 #define DEFAULT_TX_RATES 0x000F
803 #define IPW_POWER_MODE_CAM 0x00 //(always on)
804 #define IPW_POWER_INDEX_1 0x01
805 #define IPW_POWER_INDEX_2 0x02
806 #define IPW_POWER_INDEX_3 0x03
807 #define IPW_POWER_INDEX_4 0x04
808 #define IPW_POWER_INDEX_5 0x05
809 #define IPW_POWER_AUTO 0x06
810 #define IPW_POWER_MASK 0x0F
811 #define IPW_POWER_ENABLED 0x10
814 #define IPW_TX_POWER_AUTO 0
818 #define IPW_TX_POWER_MIN 0
823 #define FW_SCAN_DONOT_ASSOCIATE 0x0001 // Dont Attempt to Associate after Scan
824 #define FW_SCAN_PASSIVE 0x0008 // Force PASSSIVE Scan
826 #define REG_MIN_CHANNEL 0
829 #define REG_CHANNEL_MASK 0x00003FFF
830 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
832 #define DIVERSITY_EITHER 0 // Use both antennas
836 #define HOST_COMMAND_WAIT 0
839 #define LOCK_NONE 0
843 #define TYPE_SWEEP_ORD 0x000D
844 #define TYPE_IBSS_STTN_ORD 0x000E
845 #define TYPE_BSS_AP_ORD 0x000F
846 #define TYPE_RAW_BEACON_ENTRY 0x0010
847 #define TYPE_CALIBRATION_DATA 0x0011
848 #define TYPE_ROGUE_AP_DATA 0x0012
849 #define TYPE_ASSOCIATION_REQUEST 0x0013
850 #define TYPE_REASSOCIATION_REQUEST 0x0014
852 #define HW_FEATURE_RFKILL 0x0001
854 #define RF_KILLSWITCH_ON 0
997 // AP table entry. set to 0 if not associated
1030 IPW_ORD_POWER_MGMT_MODE, // Power mode - 0=CAM, 1=PSP
1089 IPW_ORD_STAT_RATE_LOG = 1010, //NS // 0 bytes: Rate log
1090 IPW_ORD_STAT_FIFO = 1011, //NS // 0 bytes: Fifo buffer data structures
1106 #define IPW_HOST_FW_SHARED_AREA0 0x0002f200
1107 #define IPW_HOST_FW_SHARED_AREA0_END 0x0002f510 // 0x310 bytes
1109 #define IPW_HOST_FW_SHARED_AREA1 0x0002f610
1110 #define IPW_HOST_FW_SHARED_AREA1_END 0x0002f630 // 0x20 bytes
1112 #define IPW_HOST_FW_SHARED_AREA2 0x0002fa00
1113 #define IPW_HOST_FW_SHARED_AREA2_END 0x0002fa20 // 0x20 bytes
1115 #define IPW_HOST_FW_SHARED_AREA3 0x0002fc00
1116 #define IPW_HOST_FW_SHARED_AREA3_END 0x0002fc10 // 0x10 bytes
1118 #define IPW_HOST_FW_INTERRUPT_AREA 0x0002ff80
1119 #define IPW_HOST_FW_INTERRUPT_AREA_END 0x00030000 // 0x80 bytes