Lines Matching +full:0 +full:x220000
29 #define MD_BASE 0x200000
30 #define MD_BASE_PERF 0x210000
31 #define MD_BASE_JUNK 0x220000
33 #define MD_IO_PROTECT 0x200000 /* MD and core register protection */
34 #define MD_IO_PROT_OVRRD 0x200008 /* Clear my bit in MD_IO_PROTECT */
35 #define MD_HSPEC_PROTECT 0x200010 /* BDDIR, LBOOT, RBOOT protection */
36 #define MD_MEMORY_CONFIG 0x200018 /* Memory/Directory DIMM control */
37 #define MD_REFRESH_CONTROL 0x200020 /* Memory/Directory refresh ctrl */
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
39 #define MD_MIG_DIFF_THRESH 0x200030 /* Page migr. count diff thresh. */
40 #define MD_MIG_VALUE_THRESH 0x200038 /* Page migr. count abs. thresh. */
41 #define MD_MIG_CANDIDATE 0x200040 /* Latest page migration candidate */
42 #define MD_MIG_CANDIDATE_CLR 0x200048 /* Clear page migration candidate */
43 #define MD_DIR_ERROR 0x200050 /* Directory DIMM error */
44 #define MD_DIR_ERROR_CLR 0x200058 /* Directory DIMM error clear */
45 #define MD_PROTOCOL_ERROR 0x200060 /* Directory protocol error */
46 #define MD_PROTOCOL_ERROR_CLR 0x200068 /* Directory protocol error clear */
47 #define MD_MEM_ERROR 0x200070 /* Memory DIMM error */
48 #define MD_MEM_ERROR_CLR 0x200078 /* Memory DIMM error clear */
49 #define MD_MISC_ERROR 0x200080 /* Miscellaneous MD error */
50 #define MD_MISC_ERROR_CLR 0x200088 /* Miscellaneous MD error clear */
51 #define MD_MEM_DIMM_INIT 0x200090 /* Memory DIMM mode initization. */
52 #define MD_DIR_DIMM_INIT 0x200098 /* Directory DIMM mode init. */
53 #define MD_MOQ_SIZE 0x2000a0 /* MD outgoing queue size */
54 #define MD_MLAN_CTL 0x2000a8 /* NIC (Microlan) control register */
56 #define MD_PERF_SEL 0x210000 /* Select perf monitor events */
57 #define MD_PERF_CNT0 0x210010 /* Performance counter 0 */
58 #define MD_PERF_CNT1 0x210018 /* Performance counter 1 */
59 #define MD_PERF_CNT2 0x210020 /* Performance counter 2 */
60 #define MD_PERF_CNT3 0x210028 /* Performance counter 3 */
61 #define MD_PERF_CNT4 0x210030 /* Performance counter 4 */
62 #define MD_PERF_CNT5 0x210038 /* Performance counter 5 */
64 #define MD_UREG0_0 0x220000 /* uController/UART 0 register */
65 #define MD_UREG0_1 0x220008 /* uController/UART 0 register */
66 #define MD_UREG0_2 0x220010 /* uController/UART 0 register */
67 #define MD_UREG0_3 0x220018 /* uController/UART 0 register */
68 #define MD_UREG0_4 0x220020 /* uController/UART 0 register */
69 #define MD_UREG0_5 0x220028 /* uController/UART 0 register */
70 #define MD_UREG0_6 0x220030 /* uController/UART 0 register */
71 #define MD_UREG0_7 0x220038 /* uController/UART 0 register */
73 #define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */
74 #define MD_LED0 0x220050 /* Eight-bit LED for CPU A */
75 #define MD_LED1 0x220058 /* Eight-bit LED for CPU B */
77 #define MD_UREG1_0 0x220080 /* uController/UART 1 register */
78 #define MD_UREG1_1 0x220088 /* uController/UART 1 register */
79 #define MD_UREG1_2 0x220090 /* uController/UART 1 register */
80 #define MD_UREG1_3 0x220098 /* uController/UART 1 register */
81 #define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */
82 #define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */
83 #define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */
84 #define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */
85 #define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */
86 #define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */
87 #define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */
88 #define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */
89 #define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */
90 #define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */
91 #define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
92 #define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
109 #define MD_SIZE_EMPTY 0 /* Valid in MEMORY_CONFIG */
121 #define MD_SIZE_BYTES(size) ((size) == 0 ? 0 : 0x400000L << (size))
122 #define MD_SIZE_MBYTES(size) ((size) == 0 ? 0 : 4 << (size))
150 #define MMC_BANK_ALL_MASK 0xffffff
151 #define MMC_RESET_DEFAULTS (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
152 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
153 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
154 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
156 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
165 #define MRC_COUNTER_MASK (UINT64_CAST 0xfff << 12)
166 #define MRC_CNT_THRESH_MASK 0xfff
167 #define MRC_RESET_DEFAULTS (UINT64_CAST 0x400)
172 #define MDI_SELECT_MASK (UINT64_CAST 0x0f << 32)
173 #define MDI_DIMM_MODE_MASK (UINT64_CAST 0xfff)
178 #define MMS_RP_SIZE_MASK (UINT64_CAST 0x3f << 8)
179 #define MMS_RQ_SIZE_SHFT 0
180 #define MMS_RQ_SIZE_MASK (UINT64_CAST 0x1f)
181 #define MMS_RESET_DEFAULTS (0x32 << 8 | 0x12)
189 #define MFC_ADDR_MASK (UINT64_CAST 0x3ffffff)
194 #define MLAN_PHI1_MASK (UINT64_CAST 0x7f << 27)
196 #define MLAN_PHI0_MASK (UINT64_CAST 0x7f << 27)
198 #define MLAN_PULSE_MASK (UINT64_CAST 0x3ff << 10)
200 #define MLAN_SAMPLE_MASK (UINT64_CAST 0xff << 2)
203 #define MLAN_DONE (UINT64_CAST 0x02)
204 #define MLAN_RD_DATA (UINT64_CAST 0x01)
205 #define MLAN_RESET_DEFAULTS (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
206 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
225 #define MSU_SLOTID_MASK 0xff
226 #define MSU_SN0_SLOTID_SHFT 0 /* Slot ID */
229 #define MSU_SN00_SLOTID_MASK (UINT64_CAST 0x80)
232 #define MSU_PIMM_PSC_MASK (0xf << MSU_PIMM_PSC_SHFT)
236 #define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
238 #define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
242 #define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
244 #define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
248 #define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
250 #define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
252 #define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
254 #define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
256 #define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
258 #define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
278 #define MD_DIR_SHARED (UINT64_CAST 0x0) /* 000 */
279 #define MD_DIR_POISONED (UINT64_CAST 0x1) /* 001 */
280 #define MD_DIR_EXCLUSIVE (UINT64_CAST 0x2) /* 010 */
281 #define MD_DIR_BUSY_SHARED (UINT64_CAST 0x3) /* 011 */
282 #define MD_DIR_BUSY_EXCL (UINT64_CAST 0x4) /* 100 */
283 #define MD_DIR_WAIT (UINT64_CAST 0x5) /* 101 */
284 #define MD_DIR_UNOWNED (UINT64_CAST 0x7) /* 111 */
299 * Format B: STATE = shared, FINE = 0
300 * Format C: STATE != shared (FINE must be 0)
303 #define MD_PDIR_MASK 0xffffffffffff /* Whole entry */
304 #define MD_PDIR_ECC_SHFT 0 /* ABC low or high */
305 #define MD_PDIR_ECC_MASK 0x7f
307 #define MD_PDIR_PRIO_MASK (0xf << 8)
319 #define MD_PDIR_ONECNT_MASK (0x3f << 16)
321 #define MD_PDIR_PTR_MASK (UINT64_CAST 0x7ff << 22)
323 #define MD_PDIR_VECMSB_BITMASK 0x3ffffff
329 #define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
330 #define MD_PDIR_VECLSB_BITSHFT 0
339 #define MD_PDIR_INIT_HI 0
352 #define MD_SDIR_MASK 0xffff /* Whole entry */
353 #define MD_SDIR_ECC_SHFT 0 /* AC low or high */
354 #define MD_SDIR_ECC_MASK 0x1f
363 #define MD_SDIR_PTR_MASK (0x3f << 10)
367 #define MD_SDIR_VECMSB_BITMASK 0x1f
371 #define MD_SDIR_VECLSB_BITMASK 0x7ff
372 #define MD_SDIR_VECLSB_BITSHFT 0
381 #define MD_SDIR_INIT_HI 0
386 #define MD_PROT_RW (UINT64_CAST 0x6)
387 #define MD_PROT_RO (UINT64_CAST 0x3)
388 #define MD_PROT_NO (UINT64_CAST 0x0)
389 #define MD_PROT_BAD (UINT64_CAST 0x5)
393 #define MD_PPROT_SHFT 0 /* Prot. field */
398 #define MD_PPROT_REFCNT_WIDTH 0x7ffff
406 #define MD_SPROT_SHFT 0 /* Prot. field */
411 #define MD_SPROT_REFCNT_WIDTH 0x7ff
416 #define MD_PROT_MIGMD_IREL (UINT64_CAST 0x3 << 3)
417 #define MD_PROT_MIGMD_IABS (UINT64_CAST 0x2 << 3)
418 #define MD_PROT_MIGMD_PREL (UINT64_CAST 0x1 << 3)
419 #define MD_PROT_MIGMD_OFF (UINT64_CAST 0x0 << 3)
448 #define DIRTYPE_STANDARD 0
554 ce_ovr: 1; /* 0: multiple correctable errs */
571 ce_ovr: 1; /* 0: multiple correctable errs */
593 overrun: 1; /* 0: multiple protocol errs */
741 #define DIR_ERROR_VALID_MASK 0xe000000000000000
743 #define DIR_ERROR_VALID_UCE 0x8000000000000000
744 #define DIR_ERROR_VALID_AE 0x4000000000000000
745 #define DIR_ERROR_VALID_CE 0x2000000000000000
747 #define MEM_ERROR_VALID_MASK 0xc000000000000000
749 #define MEM_ERROR_VALID_UCE 0x8000000000000000
750 #define MEM_ERROR_VALID_CE 0x4000000000000000
752 #define PROTO_ERROR_VALID_MASK 0x8000000000000000
754 #define MISC_ERROR_VALID_MASK 0x3ff
760 #define DIR_ERR_HSPEC_MASK 0x3ffffff8
761 #define ERROR_HSPEC_MASK 0x3ffffff8
763 #define ERROR_ADDR_MASK 0xfffffff8
770 #define MMCE_VALID_MASK 0x3ff
772 #define MMCE_ILL_MSG_MASK (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
774 #define MMCE_ILL_REV_MASK (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
776 #define MMCE_LONG_PACK_MASK (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
778 #define MMCE_SHORT_PACK_MASK (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
779 #define MMCE_BAD_DATA_SHFT 0
780 #define MMCE_BAD_DATA_MASK (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
786 #define MEM_DIMM_MASK 0xe0000000