Home
last modified time | relevance | path

Searched +full:0 +full:x20010000 (Results 1 – 18 of 18) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/msm/dsi/
Ddsi_cfg.h11 #define MSM_DSI_VER_MAJOR_V2 0x02
12 #define MSM_DSI_VER_MAJOR_6G 0x03
13 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000
14 #define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002
15 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000
16 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001
17 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000
18 #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000
19 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001
20 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,coresight-etb10.yaml82 reg = <0x20010000 0x1000>;
/linux-6.12.1/drivers/net/ethernet/cavium/thunder/
Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux-6.12.1/drivers/hwmon/occ/
Dp8_i2c.c19 #define OCB_DATA1 0x6B035
20 #define OCB_ADDR 0x6B070
21 #define OCB_DATA3 0x6B075
24 #define OCC_SRAM_ADDR_CMD 0xFFFF6000
25 #define OCC_SRAM_ADDR_RESP 0xFFFF7000
27 #define OCC_DATA_ATTN 0x20010000
45 msgs[0].addr = client->addr; in p8_i2c_occ_getscom()
46 msgs[0].flags = client->flags & I2C_M_TEN; in p8_i2c_occ_getscom()
47 msgs[0].len = sizeof(u32); in p8_i2c_occ_getscom()
49 msgs[0].buf = (char *)&address; in p8_i2c_occ_getscom()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramgf100.c112 u32 part = nvkm_rd32(device, 0x022438), i; in gf100_ram_train()
113 u32 mask = nvkm_rd32(device, 0x022554); in gf100_ram_train()
114 u32 addr = 0x110974; in gf100_ram_train()
116 ram_wr32(fuc, 0x10f910, magic); in gf100_ram_train()
117 ram_wr32(fuc, 0x10f914, magic); in gf100_ram_train()
119 for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) { in gf100_ram_train()
122 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); in gf100_ram_train()
149 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { in gf100_ram_calc()
162 if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) { in gf100_ram_calc()
168 strap = nvbios_rd08(bios, ramcfg.data + 0x01); in gf100_ram_calc()
[all …]
/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15_a7.dts16 arm,hbi = <0x249>;
17 arm,vexpress,site = <0xf>;
36 #size-cells = <0>;
38 cpu0: cpu@0 {
41 reg = <0>;
61 reg = <0x100>;
71 reg = <0x101>;
81 reg = <0x102>;
109 reg = <0 0x80000000 0 0x40000000>;
117 /* Chipselect 2 is physically at 0x18000000 */
[all …]
/linux-6.12.1/drivers/fsi/
Dfsi-occ.c29 #define OCC_P9_SRAM_CMD_ADDR 0xFFFBE000
30 #define OCC_P9_SRAM_RSP_ADDR 0xFFFBF000
32 #define OCC_P10_SRAM_CMD_ADDR 0xFFFFD000
33 #define OCC_P10_SRAM_RSP_ADDR 0xFFFFE000
35 #define OCC_P10_SRAM_MODE 0x58 /* Normal mode, OCB channel 2 */
104 return 0; in occ_open()
111 ssize_t rc = 0; in occ_read()
162 * byte 0: command type in occ_write()
187 client->read_offset = 0; in occ_write()
206 return 0; in occ_release()
[all …]
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3066a.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
30 reg = <0x0>;
47 reg = <0x1>;
74 reg = <0x10080000 0x10000>;
77 ranges = <0 0x10080000 0x10000>;
79 smp-sram@0 {
81 reg = <0x0 0x50>;
87 reg = <0x1010c000 0x19c>;
102 #size-cells = <0>;
[all …]
Drk3188.dtsi18 #size-cells = <0>;
21 cpu0: cpu@0 {
25 reg = <0x0>;
35 reg = <0x1>;
43 reg = <0x2>;
51 reg = <0x3>;
57 cpu0_opp_table: opp-table-0 {
104 reg = <0x10080000 0x8000>;
107 ranges = <0 0x10080000 0x8000>;
109 smp-sram@0 {
[all …]
/linux-6.12.1/drivers/media/platform/verisilicon/
Dhantro_h264.c27 * indicates the status of the picture 0.
45 0x14f10236, 0x034a14f1, 0x0236034a, 0xe47fe968, 0xfa35ff36, 0x07330000,
46 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
47 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
48 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
49 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
50 0x0029003f, 0x003f003f, 0xf7530456, 0x0061f948, 0x0d29033e, 0x000b0137,
51 0x0045ef7f, 0xf3660052, 0xf94aeb6b, 0xe57fe17f, 0xe87fee5f, 0xe57feb72,
52 0xe27fef7b, 0xf473f07a, 0xf573f43f, 0xfe44f154, 0xf368fd46, 0xf85df65a,
53 0xe27fff4a, 0xfa61f95b, 0xec7ffc38, 0xfb52f94c, 0xea7df95d, 0xf557fd4d,
[all …]
/linux-6.12.1/arch/arm64/boot/dts/arm/
Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
38 reg = <0x0 0x2b400000 0x0 0x10000>;
50 reg = <0x0 0x2b500000 0x0 0x10000>;
61 reg = <0x0 0x2b600000 0x0 0x10000>;
67 power-domains = <&scpi_devpd 0>;
72 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am62a-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
Dk3-am62-main.dtsi11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
Dk3-am62p-j722s-common-main.dtsi22 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
23 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
24 <0x01 0x00000000 0x00 0x2000>, /* GICC */
25 <0x01 0x00010000 0x00 0x1000>, /* GICH */
26 <0x01 0x00020000 0x00 0x2000>; /* GICV */
35 reg = <0x00 0x01820000 0x00 0x10000>;
36 socionext,synquacer-pre-its = <0x1000000 0x400000>;
44 reg = <0x00 0x00100000 0x00 0x20000>;
47 ranges = <0x00 0x00 0x00100000 0x20000>;
51 reg = <0x4044 0x8>;
[all …]
Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]
/linux-6.12.1/drivers/spmi/
Dspmi-pmic-arb.c23 #define PMIC_ARB_VERSION 0x0000
24 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
25 #define PMIC_ARB_VERSION_V3_MIN 0x30000000
26 #define PMIC_ARB_VERSION_V5_MIN 0x50000000
27 #define PMIC_ARB_VERSION_V7_MIN 0x70000000
28 #define PMIC_ARB_INT_EN 0x0004
30 #define PMIC_ARB_FEATURES 0x0004
31 #define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
33 #define PMIC_ARB_FEATURES1 0x0008
36 #define PMIC_ARB_CMD 0x00
[all …]
/linux-6.12.1/arch/arc/net/
Dbpf_jit_arcv2.c91 #define REG_LO(r) (bpf2arc[(r)][0])
110 ZZ_4_byte = 0,
126 AA_none = 0,
134 X_zero = 0,
140 CC_always = 0, /* condition is true all the time */
155 #define IN_U6_RANGE(x) ((x) <= (0x40 - 1) && (x) >= 0)
156 #define IN_S9_RANGE(x) ((x) <= (0x100 - 1) && (x) >= -0x100)
157 #define IN_S12_RANGE(x) ((x) <= (0x800 - 1) && (x) >= -0x800)
158 #define IN_S21_RANGE(x) ((x) <= (0x100000 - 1) && (x) >= -0x100000)
159 #define IN_S25_RANGE(x) ((x) <= (0x1000000 - 1) && (x) >= -0x1000000)
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]