Lines Matching +full:0 +full:x20010000
23 #define PMIC_ARB_VERSION 0x0000
24 #define PMIC_ARB_VERSION_V2_MIN 0x20010000
25 #define PMIC_ARB_VERSION_V3_MIN 0x30000000
26 #define PMIC_ARB_VERSION_V5_MIN 0x50000000
27 #define PMIC_ARB_VERSION_V7_MIN 0x70000000
28 #define PMIC_ARB_INT_EN 0x0004
30 #define PMIC_ARB_FEATURES 0x0004
31 #define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)
33 #define PMIC_ARB_FEATURES1 0x0008
36 #define PMIC_ARB_CMD 0x00
37 #define PMIC_ARB_CONFIG 0x04
38 #define PMIC_ARB_STATUS 0x08
39 #define PMIC_ARB_WDATA0 0x10
40 #define PMIC_ARB_WDATA1 0x14
41 #define PMIC_ARB_RDATA0 0x18
42 #define PMIC_ARB_RDATA1 0x1C
45 #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))
46 #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)
47 #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)
48 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
49 #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)
50 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
56 #define INVALID_EE 0xFF
59 #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)
63 PMIC_ARB_STATUS_DONE = BIT(0),
74 PMIC_ARB_OP_EXT_WRITEL = 0,
107 #define PMIC_ARB_APID_MASK 0xFF
108 #define PMIC_ARB_PPID_MASK 0xFFF
111 #define SPMI_PIC_ACC_ENABLE_BIT BIT(0)
114 ((((slave_id) & 0xF) << 28) | \
115 (((periph_id) & 0xFF) << 20) | \
116 (((irq_id) & 0x7) << 16) | \
117 (((apid) & 0x3FF) << 0))
119 #define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
120 #define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
121 #define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
122 #define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
262 * @bc: byte count -1. range: 0..3
277 * @bc: byte-count -1. range: 0..3.
284 u32 data = 0; in pmic_arb_write_data()
296 u32 status = 0; in pmic_arb_wait_for_done()
302 if (rc < 0) in pmic_arb_wait_for_done()
319 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n", in pmic_arb_wait_for_done()
331 return 0; in pmic_arb_wait_for_done()
351 rc = pmic_arb->ver_ops->offset(bus, sid, 0, PMIC_ARB_CHANNEL_RW); in pmic_arb_non_data_cmd_v1()
352 if (rc < 0) in pmic_arb_non_data_cmd_v1()
356 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); in pmic_arb_non_data_cmd_v1()
360 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0, in pmic_arb_non_data_cmd_v1()
378 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); in pmic_arb_cmd()
396 if (rc < 0) in pmic_arb_fmt_read_cmd()
407 if (opc >= 0x60 && opc <= 0x7F) in pmic_arb_fmt_read_cmd()
409 else if (opc >= 0x20 && opc <= 0x2F) in pmic_arb_fmt_read_cmd()
411 else if (opc >= 0x38 && opc <= 0x3F) in pmic_arb_fmt_read_cmd()
418 return 0; in pmic_arb_fmt_read_cmd()
442 return 0; in pmic_arb_read_cmd_unlocked()
475 if (rc < 0) in pmic_arb_fmt_write_cmd()
486 if (opc >= 0x40 && opc <= 0x5F) in pmic_arb_fmt_write_cmd()
488 else if (opc <= 0x0F) in pmic_arb_fmt_write_cmd()
490 else if (opc >= 0x30 && opc <= 0x37) in pmic_arb_fmt_write_cmd()
492 else if (opc >= 0x80) in pmic_arb_fmt_write_cmd()
499 return 0; in pmic_arb_fmt_write_cmd()
569 for (i = 0; i < len; i++) in pmic_arb_masked_write()
581 QPNPINT_REG_RT_STS = 0x10,
582 QPNPINT_REG_SET_TYPE = 0x11,
583 QPNPINT_REG_POLARITY_HIGH = 0x12,
584 QPNPINT_REG_POLARITY_LOW = 0x13,
585 QPNPINT_REG_LATCHED_CLR = 0x14,
586 QPNPINT_REG_EN_SET = 0x15,
587 QPNPINT_REG_EN_CLR = 0x16,
588 QPNPINT_REG_LATCHED_STS = 0x18,
645 u8 per = ppid & 0xFF; in cleanup_irq()
648 dev_err_ratelimited(&bus->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", in cleanup_irq()
658 int handled = 0; in periph_interrupt()
659 u8 sid = (bus->apid_data[apid].ppid >> 8) & 0xF; in periph_interrupt()
660 u8 per = bus->apid_data[apid].ppid & 0xFF; in periph_interrupt()
668 if (irq == 0) { in periph_interrupt()
693 u32 status, enable, handled = 0; in pmic_arb_chained_irq()
697 u32 irq_status = 0; in pmic_arb_chained_irq()
718 if (periph_interrupt(bus, apid) != 0) in pmic_arb_chained_irq()
739 if (periph_interrupt(bus, i) != 0) in pmic_arb_chained_irq()
746 if (handled == 0) in pmic_arb_chained_irq()
786 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); in qpnpint_irq_unmask()
787 if (!(buf[0] & BIT(irq))) { in qpnpint_irq_unmask()
793 buf[0] = BIT(irq); in qpnpint_irq_unmask()
801 struct spmi_pmic_arb_qpnpint_type type = {0}; in qpnpint_irq_set_type()
851 u8 status = 0; in qpnpint_get_irqchip_state()
859 return 0; in qpnpint_get_irqchip_state()
884 return 0; in qpnpint_irq_domain_activate()
909 dev_dbg(&bus->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", in qpnpint_irq_domain_translate()
910 intspec[0], intspec[1], intspec[2]); in qpnpint_irq_domain_translate()
916 if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7) in qpnpint_irq_domain_translate()
919 ppid = intspec[0] << 8 | intspec[1]; in qpnpint_irq_domain_translate()
921 if (rc < 0) { in qpnpint_irq_domain_translate()
923 intspec[0], intspec[1], intspec[2], rc); in qpnpint_irq_domain_translate()
934 *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid); in qpnpint_irq_domain_translate()
939 return 0; in qpnpint_irq_domain_translate()
979 for (i = 0; i < nr_irqs; i++) in qpnpint_irq_domain_alloc()
983 return 0; in qpnpint_irq_domain_alloc()
994 bus->max_apid = 0; in pmic_arb_init_apid_min_max()
997 return 0; in pmic_arb_init_apid_min_max()
1010 return 0; in pmic_arb_get_core_resources_v1()
1037 int index = 0, i; in pmic_arb_ppid_to_apid_v1()
1048 for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { in pmic_arb_ppid_to_apid_v1()
1086 return 0x800 + 0x80 * pmic_arb->channel; in pmic_arb_offset_v1()
1135 return 0; in pmic_arb_get_obsrvr_chnls_v2()
1181 * the primary bus (0) and secondary bus (1) such that: in pmic_arb_read_apid_map_v5()
1182 * APID = 0 to N-1 are assigned to the primary bus in pmic_arb_read_apid_map_v5()
1227 for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { in pmic_arb_read_apid_map_v5()
1237 return 0; in pmic_arb_read_apid_map_v5()
1257 ppid = sid << 8 | ((addr >> 8) & 0xFF); in pmic_arb_offset_v2()
1259 if (rc < 0) in pmic_arb_offset_v2()
1263 return 0x1000 * pmic_arb->ee + 0x8000 * apid; in pmic_arb_offset_v2()
1277 bus->base_apid = 0; in pmic_arb_init_apid_v5()
1298 return 0; in pmic_arb_init_apid_v5()
1311 u32 offset = 0; in pmic_arb_offset_v5()
1315 if (rc < 0) in pmic_arb_offset_v5()
1321 offset = 0x10000 * pmic_arb->ee + 0x80 * apid; in pmic_arb_offset_v5()
1325 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", in pmic_arb_offset_v5()
1329 offset = 0x10000 * apid; in pmic_arb_offset_v5()
1357 if (index == 0) { in pmic_arb_init_apid_v7()
1358 bus->base_apid = 0; in pmic_arb_init_apid_v7()
1389 return 0; in pmic_arb_init_apid_v7()
1402 u32 offset = 0; in pmic_arb_offset_v7()
1406 if (rc < 0) in pmic_arb_offset_v7()
1412 offset = 0x8000 * pmic_arb->ee + 0x20 * apid; in pmic_arb_offset_v7()
1416 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", in pmic_arb_offset_v7()
1420 offset = 0x1000 * apid; in pmic_arb_offset_v7()
1429 return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); in pmic_arb_fmt_cmd_v1()
1434 return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); in pmic_arb_fmt_cmd_v2()
1440 return bus->intr + 0x20 * m + 0x4 * n; in pmic_arb_owner_acc_status_v1()
1446 return bus->intr + 0x100000 + 0x1000 * m + 0x4 * n; in pmic_arb_owner_acc_status_v2()
1452 return bus->intr + 0x200000 + 0x1000 * m + 0x4 * n; in pmic_arb_owner_acc_status_v3()
1458 return bus->intr + 0x10000 * m + 0x4 * n; in pmic_arb_owner_acc_status_v5()
1464 return bus->intr + 0x1000 * m + 0x4 * n; in pmic_arb_owner_acc_status_v7()
1470 return bus->intr + 0x200 + 0x4 * n; in pmic_arb_acc_enable_v1()
1476 return bus->intr + 0x1000 * n; in pmic_arb_acc_enable_v2()
1483 return pmic_arb->wr_base + 0x100 + 0x10000 * n; in pmic_arb_acc_enable_v5()
1490 return pmic_arb->wr_base + 0x100 + 0x1000 * n; in pmic_arb_acc_enable_v7()
1496 return bus->intr + 0x600 + 0x4 * n; in pmic_arb_irq_status_v1()
1502 return bus->intr + 0x4 + 0x1000 * n; in pmic_arb_irq_status_v2()
1509 return pmic_arb->wr_base + 0x104 + 0x10000 * n; in pmic_arb_irq_status_v5()
1516 return pmic_arb->wr_base + 0x104 + 0x1000 * n; in pmic_arb_irq_status_v7()
1522 return bus->intr + 0xA00 + 0x4 * n; in pmic_arb_irq_clear_v1()
1528 return bus->intr + 0x8 + 0x1000 * n; in pmic_arb_irq_clear_v2()
1535 return pmic_arb->wr_base + 0x108 + 0x10000 * n; in pmic_arb_irq_clear_v5()
1542 return pmic_arb->wr_base + 0x108 + 0x1000 * n; in pmic_arb_irq_clear_v7()
1547 return 0x800 + 0x4 * n; in pmic_arb_apid_map_offset_v2()
1552 return 0x900 + 0x4 * n; in pmic_arb_apid_map_offset_v5()
1557 return 0x2000 + 0x4 * n; in pmic_arb_apid_map_offset_v7()
1563 return bus->cnfg + 0x700 + 0x4 * n; in pmic_arb_apid_owner_v2()
1569 * 0.
1574 return bus->cnfg + 0x4 * (n - bus->base_apid); in pmic_arb_apid_owner_v7()
1704 if (index < 0) { in spmi_pmic_arb_bus_init()
1714 if (index < 0) { in spmi_pmic_arb_bus_init()
1724 if (irq <= 0) in spmi_pmic_arb_bus_init()
1758 return 0; in spmi_pmic_arb_bus_init()
1788 for (i = 0; i < pmic_arb->buses_available; i++) { in spmi_pmic_arb_deregister_buses()
1836 dev_info(dev, "PMIC arbiter version %s (0x%x)\n", in spmi_pmic_arb_probe()