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/linux-6.12.1/arch/mips/boot/dts/loongson/
Dloongson64g-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
22 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
26 reg = <0 0x3ff01400 0x64>;
35 loongson,parent_int_map = <0x00ffffff>, /* int0 */
36 <0xff000000>, /* int1 */
37 <0x00000000>, /* int2 */
38 <0x00000000>; /* int3 */
44 reg = <0 0x1fe00100 0x10>;
[all …]
Dloongson64c-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44 0 0x40000000 0 0x40000000 0 0x40000000
45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
51 ranges = <1 0x0 0x0 0x18000000 0x4000>;
56 reg = <0 0x1fe07000 0 0x422>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/airoha/
Den7581-evb.dts5 /memreserve/ 0x80000000 0x200000;
19 linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>;
24 reg = <0x0 0x80000000 0x2 0x00000000>;
/linux-6.12.1/arch/arm/boot/dts/airoha/
Den7523-evb.dts5 /memreserve/ 0x80000000 0x200000;
20 linux,usable-memory-range = <0x80200000 0x1fe00000>;
25 reg = <0x80000000 0x20000000>;
/linux-6.12.1/Documentation/devicetree/bindings/hwinfo/
Dloongson,ls2k-chipid.yaml36 reg = <0x1fe00000 0x3ffc>;
/linux-6.12.1/arch/mips/include/asm/mach-loongson32/
Dloongson1.h18 #define LS1X_MUX_BASE 0x1fd00420
19 #define LS1X_INTC_BASE 0x1fd01040
20 #define LS1X_GPIO0_BASE 0x1fd010c0
21 #define LS1X_GPIO1_BASE 0x1fd010c4
22 #define LS1X_DMAC_BASE 0x1fd01160
23 #define LS1X_CBUS_BASE 0x1fd011c0
24 #define LS1X_EHCI_BASE 0x1fe00000
25 #define LS1X_OHCI_BASE 0x1fe08000
26 #define LS1X_GMAC0_BASE 0x1fe10000
27 #define LS1X_GMAC1_BASE 0x1fe20000
[all …]
/linux-6.12.1/arch/loongarch/include/asm/
Dloongson.h20 #define LOONGSON_LIO_BASE 0x18000000
21 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
24 #define LOONGSON_BOOT_BASE 0x1c000000
25 #define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
28 #define LOONGSON_REG_BASE 0x1fe00000
29 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */
34 #define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
35 #define LOONGSON_GPIOIE LOONGSON_REG(0x120)
36 #define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
46 " st.w %[v], %[hw], 0 \n" in xconf_writel()
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dreg_mci.h20 #define AR_MCI_COMMAND0 0x1800
21 #define AR_MCI_COMMAND0_HEADER 0xFF
22 #define AR_MCI_COMMAND0_HEADER_S 0
23 #define AR_MCI_COMMAND0_LEN 0x1f00
25 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000
28 #define AR_MCI_COMMAND1 0x1804
30 #define AR_MCI_COMMAND2 0x1808
31 #define AR_MCI_COMMAND2_RESET_TX 0x01
32 #define AR_MCI_COMMAND2_RESET_TX_S 0
33 #define AR_MCI_COMMAND2_RESET_RX 0x02
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-loongson64/
Dloongson_regs.h25 "parse_r __res,%0\n\t" in read_cpucfg()
29 ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" in read_cpucfg()
38 #define LOONGSON_CFG0 0x0
39 #define LOONGSON_CFG0_PRID GENMASK(31, 0)
41 #define LOONGSON_CFG1 0x1
42 #define LOONGSON_CFG1_FP BIT(0)
74 #define LOONGSON_CFG2 0x2
75 #define LOONGSON_CFG2_LEXT1 BIT(0)
104 #define LOONGSON_CFG3 0x3
105 #define LOONGSON_CFG3_LCAMP BIT(0)
[all …]
Dloongson.h62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
90 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-loongson2ef/
Dloongson.h51 for (x = 0; x < 100000; x++) \
60 #define LOONGSON_FLASH_BASE 0x1c000000
61 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
64 #define LOONGSON_LIO0_BASE 0x1e000000
65 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
68 #define LOONGSON_BOOT_BASE 0x1fc00000
69 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
71 #define LOONGSON_REG_BASE 0x1fe00000
72 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
75 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
/linux-6.12.1/arch/mips/include/asm/mips-boards/
Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dmsm8994-sony-xperia-kitakami.dtsi16 * We support MSM8994 v2 (0x20000) and v2.1 (0x20001).
17 * The V1 chip (0x0 and 0x10000) is significantly different
21 qcom,msm-id = <207 0x20000>, <207 0x20001>;
23 qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>;
25 qcom,board-id = <8 0>;
34 button-0 {
75 reg = <0 0x1fe00000 0 0x200000>;
76 console-size = <0x100000>;
77 record-size = <0x10000>;
78 ftrace-size = <0x10000>;
[all …]
/linux-6.12.1/drivers/scsi/bfa/
Dbfi_reg.h18 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
19 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
20 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
21 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
22 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
23 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
24 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
25 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
27 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
28 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux-6.12.1/drivers/net/ethernet/brocade/bna/
Dbfi_reg.h19 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
20 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
21 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
22 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
23 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
24 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
25 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
26 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
28 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
29 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux-6.12.1/arch/loongarch/boot/dts/
Dloongson-2k1000.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg= <0x0>;
30 reg = <0x1>;
37 #clock-cells = <0>;
49 i2c-gpio-0 {
51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55 #size-cells = <0>;
66 #size-cells = <0>;
74 thermal-sensors = <&tsensor 0>;
[all …]
/linux-6.12.1/drivers/net/ethernet/ti/
Dtlan.h40 #define TLAN_IGNORE 0
47 } while (0)
49 #define TLAN_DEBUG_GNRL 0x0001
50 #define TLAN_DEBUG_TX 0x0002
51 #define TLAN_DEBUG_RX 0x0004
52 #define TLAN_DEBUG_LIST 0x0008
53 #define TLAN_DEBUG_PROBE 0x0010
65 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
66 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
68 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
[all …]
/linux-6.12.1/drivers/net/can/sja1000/
Dsja1000.c101 return (priv->read_reg(priv, SJA1000_MOD) == 0xFF); in sja1000_is_absent()
110 return 0; in sja1000_probe_chip()
124 for (i = 0; i < 100; i++) { in set_reset_mode()
144 u8 mod_reg_val = 0x00; in set_normal_mode()
147 for (i = 0; i < 100; i++) { in set_normal_mode()
149 if ((status & MOD_RM) == 0) { in set_normal_mode()
192 priv->write_reg(priv, SJA1000_ACCC0, 0x00); in chipset_init()
193 priv->write_reg(priv, SJA1000_ACCC1, 0x00); in chipset_init()
194 priv->write_reg(priv, SJA1000_ACCC2, 0x00); in chipset_init()
195 priv->write_reg(priv, SJA1000_ACCC3, 0x00); in chipset_init()
[all …]
/linux-6.12.1/drivers/net/ethernet/freescale/
Dgianfar.h70 #define MAX_TX_QS 0x8
71 #define MAX_RX_QS 0x8
74 #define MAXGROUPS 0x2
99 #define DEFAULT_FIFO_TX_THR 0x100
100 #define DEFAULT_FIFO_TX_STARVE 0x40
101 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
126 #define DEFAULT_RX_COALESCE 0
127 #define DEFAULT_RXCOUNT 0
130 #define MII_TBICON 0x11
133 #define TBICON_CLK_SELECT 0x0020
[all …]
/linux-6.12.1/drivers/net/can/
Djanz-ican3.c30 #define QUEUE_OLD_CONTROL 0
37 #define MSYNC_PEER 0x00 /* ICAN only */
38 #define MSYNC_LOCL 0x01 /* host only */
39 #define TARGET_RUNNING 0x02
40 #define FIRMWARE_STAMP 0x60 /* big endian firmware stamp */
42 #define MSYNC_RB0 0x01
43 #define MSYNC_RB1 0x02
44 #define MSYNC_RBLW 0x04
47 #define MSYNC_WB0 0x10
48 #define MSYNC_WB1 0x20
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]