Lines Matching +full:0 +full:x1fe00000
70 #define MAX_TX_QS 0x8
71 #define MAX_RX_QS 0x8
74 #define MAXGROUPS 0x2
99 #define DEFAULT_FIFO_TX_THR 0x100
100 #define DEFAULT_FIFO_TX_STARVE 0x40
101 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
126 #define DEFAULT_RX_COALESCE 0
127 #define DEFAULT_RXCOUNT 0
130 #define MII_TBICON 0x11
133 #define TBICON_CLK_SELECT 0x0020
136 #define MACCFG1_SOFT_RESET 0x80000000
137 #define MACCFG1_RESET_RX_MC 0x00080000
138 #define MACCFG1_RESET_TX_MC 0x00040000
139 #define MACCFG1_RESET_RX_FUN 0x00020000
140 #define MACCFG1_RESET_TX_FUN 0x00010000
141 #define MACCFG1_LOOPBACK 0x00000100
142 #define MACCFG1_RX_FLOW 0x00000020
143 #define MACCFG1_TX_FLOW 0x00000010
144 #define MACCFG1_SYNCD_RX_EN 0x00000008
145 #define MACCFG1_RX_EN 0x00000004
146 #define MACCFG1_SYNCD_TX_EN 0x00000002
147 #define MACCFG1_TX_EN 0x00000001
149 #define MACCFG2_INIT_SETTINGS 0x00007205
150 #define MACCFG2_FULL_DUPLEX 0x00000001
151 #define MACCFG2_IF 0x00000300
152 #define MACCFG2_MII 0x00000100
153 #define MACCFG2_GMII 0x00000200
154 #define MACCFG2_HUGEFRAME 0x00000020
155 #define MACCFG2_LENGTHCHECK 0x00000010
156 #define MACCFG2_MPEN 0x00000008
158 #define ECNTRL_FIFM 0x00008000
159 #define ECNTRL_INIT_SETTINGS 0x00001000
160 #define ECNTRL_TBI_MODE 0x00000020
161 #define ECNTRL_REDUCED_MODE 0x00000010
162 #define ECNTRL_R100 0x00000008
163 #define ECNTRL_REDUCED_MII_MODE 0x00000004
164 #define ECNTRL_SGMII_MODE 0x00000002
166 #define MINFLR_INIT_SETTINGS 0x00000040
169 #define TQUEUE_EN0 0x00008000
170 #define TQUEUE_EN1 0x00004000
171 #define TQUEUE_EN2 0x00002000
172 #define TQUEUE_EN3 0x00001000
173 #define TQUEUE_EN4 0x00000800
174 #define TQUEUE_EN5 0x00000400
175 #define TQUEUE_EN6 0x00000200
176 #define TQUEUE_EN7 0x00000100
177 #define TQUEUE_EN_ALL 0x0000FF00
179 #define TR03WT_WT0_MASK 0xFF000000
180 #define TR03WT_WT1_MASK 0x00FF0000
181 #define TR03WT_WT2_MASK 0x0000FF00
182 #define TR03WT_WT3_MASK 0x000000FF
184 #define TR47WT_WT4_MASK 0xFF000000
185 #define TR47WT_WT5_MASK 0x00FF0000
186 #define TR47WT_WT6_MASK 0x0000FF00
187 #define TR47WT_WT7_MASK 0x000000FF
190 #define RQUEUE_EX0 0x00800000
191 #define RQUEUE_EX1 0x00400000
192 #define RQUEUE_EX2 0x00200000
193 #define RQUEUE_EX3 0x00100000
194 #define RQUEUE_EX4 0x00080000
195 #define RQUEUE_EX5 0x00040000
196 #define RQUEUE_EX6 0x00020000
197 #define RQUEUE_EX7 0x00010000
198 #define RQUEUE_EX_ALL 0x00FF0000
200 #define RQUEUE_EN0 0x00000080
201 #define RQUEUE_EN1 0x00000040
202 #define RQUEUE_EN2 0x00000020
203 #define RQUEUE_EN3 0x00000010
204 #define RQUEUE_EN4 0x00000008
205 #define RQUEUE_EN5 0x00000004
206 #define RQUEUE_EN6 0x00000002
207 #define RQUEUE_EN7 0x00000001
208 #define RQUEUE_EN_ALL 0x000000FF
211 #define DMACTRL_INIT_SETTINGS 0x000000c3
212 #define DMACTRL_GRS 0x00000010
213 #define DMACTRL_GTS 0x00000008
215 #define TSTAT_CLEAR_THALT_ALL 0xFF000000
216 #define TSTAT_CLEAR_THALT 0x80000000
217 #define TSTAT_CLEAR_THALT0 0x80000000
218 #define TSTAT_CLEAR_THALT1 0x40000000
219 #define TSTAT_CLEAR_THALT2 0x20000000
220 #define TSTAT_CLEAR_THALT3 0x10000000
221 #define TSTAT_CLEAR_THALT4 0x08000000
222 #define TSTAT_CLEAR_THALT5 0x04000000
223 #define TSTAT_CLEAR_THALT6 0x02000000
224 #define TSTAT_CLEAR_THALT7 0x01000000
227 #define IC_ICEN 0x80000000
228 #define IC_ICFT_MASK 0x1fe00000
232 #define IC_ICTT_MASK 0x0000ffff
245 #define RCTRL_TS_ENABLE 0x01000000
246 #define RCTRL_PAL_MASK 0x001f0000
247 #define RCTRL_LFC 0x00004000
248 #define RCTRL_VLEX 0x00002000
249 #define RCTRL_FILREN 0x00001000
250 #define RCTRL_GHTX 0x00000400
251 #define RCTRL_IPCSEN 0x00000200
252 #define RCTRL_TUCSEN 0x00000100
253 #define RCTRL_PRSDEP_MASK 0x000000c0
254 #define RCTRL_PRSDEP_INIT 0x000000c0
255 #define RCTRL_PRSFM 0x00000020
256 #define RCTRL_PROM 0x00000008
257 #define RCTRL_EMEN 0x00000002
267 #define RSTAT_CLEAR_RHALT 0x00800000
268 #define RSTAT_CLEAR_RXF0 0x00000080
269 #define RSTAT_RXF_MASK 0x000000ff
271 #define TCTRL_IPCSEN 0x00004000
272 #define TCTRL_TUCSEN 0x00002000
273 #define TCTRL_VLINS 0x00001000
274 #define TCTRL_THDF 0x00000800
275 #define TCTRL_RFCPAUSE 0x00000010
276 #define TCTRL_TFCPAUSE 0x00000008
277 #define TCTRL_TXSCHED_MASK 0x00000006
278 #define TCTRL_TXSCHED_INIT 0x00000000
280 #define TCTRL_TXSCHED_PRIO 0x00000002
282 #define TCTRL_TXSCHED_WRRS 0x00000004
287 #define DEFAULT_WRRS_WEIGHT 0x18181818
291 #define IEVENT_INIT_CLEAR 0xffffffff
292 #define IEVENT_BABR 0x80000000
293 #define IEVENT_RXC 0x40000000
294 #define IEVENT_BSY 0x20000000
295 #define IEVENT_EBERR 0x10000000
296 #define IEVENT_MSRO 0x04000000
297 #define IEVENT_GTSC 0x02000000
298 #define IEVENT_BABT 0x01000000
299 #define IEVENT_TXC 0x00800000
300 #define IEVENT_TXE 0x00400000
301 #define IEVENT_TXB 0x00200000
302 #define IEVENT_TXF 0x00100000
303 #define IEVENT_LC 0x00040000
304 #define IEVENT_CRL 0x00020000
305 #define IEVENT_XFUN 0x00010000
306 #define IEVENT_RXB0 0x00008000
307 #define IEVENT_MAG 0x00000800
308 #define IEVENT_GRSC 0x00000100
309 #define IEVENT_RXF0 0x00000080
310 #define IEVENT_FGPI 0x00000010
311 #define IEVENT_FIR 0x00000008
312 #define IEVENT_FIQ 0x00000004
313 #define IEVENT_DPE 0x00000002
314 #define IEVENT_PERR 0x00000001
324 #define IMASK_INIT_CLEAR 0x00000000
325 #define IMASK_BABR 0x80000000
326 #define IMASK_RXC 0x40000000
327 #define IMASK_BSY 0x20000000
328 #define IMASK_EBERR 0x10000000
329 #define IMASK_MSRO 0x04000000
330 #define IMASK_GTSC 0x02000000
331 #define IMASK_BABT 0x01000000
332 #define IMASK_TXC 0x00800000
333 #define IMASK_TXEEN 0x00400000
334 #define IMASK_TXBEN 0x00200000
335 #define IMASK_TXFEN 0x00100000
336 #define IMASK_LC 0x00040000
337 #define IMASK_CRL 0x00020000
338 #define IMASK_XFUN 0x00010000
339 #define IMASK_RXB0 0x00008000
340 #define IMASK_MAG 0x00000800
341 #define IMASK_GRSC 0x00000100
342 #define IMASK_RXFEN0 0x00000080
343 #define IMASK_FGPI 0x00000010
344 #define IMASK_FIR 0x00000008
345 #define IMASK_FIQ 0x00000004
346 #define IMASK_DPE 0x00000002
347 #define IMASK_PERR 0x00000001
361 #define ATTR_BDSTASH 0x00000800
363 #define ATTR_BUFSTASH 0x00004000
365 #define ATTR_SNOOPING 0x000000c0
368 #define ATTRELI_INIT_SETTINGS 0x0
369 #define ATTRELI_EL_MASK 0x3fff0000
371 #define ATTRELI_EI_MASK 0x00003fff
375 #define BD_LENGTH_MASK 0x0000ffff
377 #define FPR_FILER_MASK 0xFFFFFFFF
378 #define MAX_FILER_IDX 0xFF
382 #define DEFAULT_8RXQ_RIR0 0x05397700
384 #define DEFAULT_2RXQ_RIR0 0x04104100
387 #define RQFCR_GPI 0x80000000
388 #define RQFCR_HASHTBL_Q 0x00000000
389 #define RQFCR_HASHTBL_0 0x00020000
390 #define RQFCR_HASHTBL_1 0x00040000
391 #define RQFCR_HASHTBL_2 0x00060000
392 #define RQFCR_HASHTBL_3 0x00080000
393 #define RQFCR_HASH 0x00010000
394 #define RQFCR_QUEUE 0x0000FC00
395 #define RQFCR_CLE 0x00000200
396 #define RQFCR_RJE 0x00000100
397 #define RQFCR_AND 0x00000080
398 #define RQFCR_CMP_EXACT 0x00000000
399 #define RQFCR_CMP_MATCH 0x00000020
400 #define RQFCR_CMP_NOEXACT 0x00000040
401 #define RQFCR_CMP_NOMATCH 0x00000060
404 #define RQFCR_PID_MASK 0x00000000
405 #define RQFCR_PID_PARSE 0x00000001
406 #define RQFCR_PID_ARB 0x00000002
407 #define RQFCR_PID_DAH 0x00000003
408 #define RQFCR_PID_DAL 0x00000004
409 #define RQFCR_PID_SAH 0x00000005
410 #define RQFCR_PID_SAL 0x00000006
411 #define RQFCR_PID_ETY 0x00000007
412 #define RQFCR_PID_VID 0x00000008
413 #define RQFCR_PID_PRI 0x00000009
414 #define RQFCR_PID_TOS 0x0000000A
415 #define RQFCR_PID_L4P 0x0000000B
416 #define RQFCR_PID_DIA 0x0000000C
417 #define RQFCR_PID_SIA 0x0000000D
418 #define RQFCR_PID_DPT 0x0000000E
419 #define RQFCR_PID_SPT 0x0000000F
421 /* RQFPR when PID is 0x0001 */
422 #define RQFPR_HDR_GE_512 0x00200000
423 #define RQFPR_LERR 0x00100000
424 #define RQFPR_RAR 0x00080000
425 #define RQFPR_RARQ 0x00040000
426 #define RQFPR_AR 0x00020000
427 #define RQFPR_ARQ 0x00010000
428 #define RQFPR_EBC 0x00008000
429 #define RQFPR_VLN 0x00004000
430 #define RQFPR_CFI 0x00002000
431 #define RQFPR_JUM 0x00001000
432 #define RQFPR_IPF 0x00000800
433 #define RQFPR_FIF 0x00000400
434 #define RQFPR_IPV4 0x00000200
435 #define RQFPR_IPV6 0x00000100
436 #define RQFPR_ICC 0x00000080
437 #define RQFPR_ICV 0x00000040
438 #define RQFPR_TCP 0x00000020
439 #define RQFPR_UDP 0x00000010
440 #define RQFPR_TUC 0x00000008
441 #define RQFPR_TUV 0x00000004
442 #define RQFPR_PER 0x00000002
443 #define RQFPR_EER 0x00000001
446 #define CAR1_C164 0x80000000
447 #define CAR1_C1127 0x40000000
448 #define CAR1_C1255 0x20000000
449 #define CAR1_C1511 0x10000000
450 #define CAR1_C11K 0x08000000
451 #define CAR1_C1MAX 0x04000000
452 #define CAR1_C1MGV 0x02000000
453 #define CAR1_C1REJ 0x00020000
454 #define CAR1_C1RBY 0x00010000
455 #define CAR1_C1RPK 0x00008000
456 #define CAR1_C1RFC 0x00004000
457 #define CAR1_C1RMC 0x00002000
458 #define CAR1_C1RBC 0x00001000
459 #define CAR1_C1RXC 0x00000800
460 #define CAR1_C1RXP 0x00000400
461 #define CAR1_C1RXU 0x00000200
462 #define CAR1_C1RAL 0x00000100
463 #define CAR1_C1RFL 0x00000080
464 #define CAR1_C1RCD 0x00000040
465 #define CAR1_C1RCS 0x00000020
466 #define CAR1_C1RUN 0x00000010
467 #define CAR1_C1ROV 0x00000008
468 #define CAR1_C1RFR 0x00000004
469 #define CAR1_C1RJB 0x00000002
470 #define CAR1_C1RDR 0x00000001
473 #define CAM1_M164 0x80000000
474 #define CAM1_M1127 0x40000000
475 #define CAM1_M1255 0x20000000
476 #define CAM1_M1511 0x10000000
477 #define CAM1_M11K 0x08000000
478 #define CAM1_M1MAX 0x04000000
479 #define CAM1_M1MGV 0x02000000
480 #define CAM1_M1REJ 0x00020000
481 #define CAM1_M1RBY 0x00010000
482 #define CAM1_M1RPK 0x00008000
483 #define CAM1_M1RFC 0x00004000
484 #define CAM1_M1RMC 0x00002000
485 #define CAM1_M1RBC 0x00001000
486 #define CAM1_M1RXC 0x00000800
487 #define CAM1_M1RXP 0x00000400
488 #define CAM1_M1RXU 0x00000200
489 #define CAM1_M1RAL 0x00000100
490 #define CAM1_M1RFL 0x00000080
491 #define CAM1_M1RCD 0x00000040
492 #define CAM1_M1RCS 0x00000020
493 #define CAM1_M1RUN 0x00000010
494 #define CAM1_M1ROV 0x00000008
495 #define CAM1_M1RFR 0x00000004
496 #define CAM1_M1RJB 0x00000002
497 #define CAM1_M1RDR 0x00000001
500 #define TXBD_READY 0x8000
501 #define TXBD_PADCRC 0x4000
502 #define TXBD_WRAP 0x2000
503 #define TXBD_INTERRUPT 0x1000
504 #define TXBD_LAST 0x0800
505 #define TXBD_CRC 0x0400
506 #define TXBD_DEF 0x0200
507 #define TXBD_HUGEFRAME 0x0080
508 #define TXBD_LATECOLLISION 0x0080
509 #define TXBD_RETRYLIMIT 0x0040
510 #define TXBD_RETRYCOUNTMASK 0x003c
511 #define TXBD_UNDERRUN 0x0002
512 #define TXBD_TOE 0x0002
515 #define TXFCB_VLN 0x80
516 #define TXFCB_IP 0x40
517 #define TXFCB_IP6 0x20
518 #define TXFCB_TUP 0x10
519 #define TXFCB_UDP 0x08
520 #define TXFCB_CIP 0x04
521 #define TXFCB_CTU 0x02
522 #define TXFCB_NPH 0x01
526 #define RXBD_EMPTY 0x8000
527 #define RXBD_RO1 0x4000
528 #define RXBD_WRAP 0x2000
529 #define RXBD_INTERRUPT 0x1000
530 #define RXBD_LAST 0x0800
531 #define RXBD_FIRST 0x0400
532 #define RXBD_MISS 0x0100
533 #define RXBD_BROADCAST 0x0080
534 #define RXBD_MULTICAST 0x0040
535 #define RXBD_LARGE 0x0020
536 #define RXBD_NONOCTET 0x0010
537 #define RXBD_SHORT 0x0008
538 #define RXBD_CRCERR 0x0004
539 #define RXBD_OVERRUN 0x0002
540 #define RXBD_TRUNCATED 0x0001
541 #define RXBD_STATS 0x01ff
547 #define RXFCB_VLN 0x8000
548 #define RXFCB_IP 0x4000
549 #define RXFCB_IP6 0x2000
550 #define RXFCB_TUP 0x1000
551 #define RXFCB_CIP 0x0800
552 #define RXFCB_CTU 0x0400
553 #define RXFCB_EIP 0x0200
554 #define RXFCB_ETU 0x0100
555 #define RXFCB_CSUM_MASK 0x0f00
556 #define RXFCB_PERR_MASK 0x000c
557 #define RXFCB_PERR_BADL3 0x0008
561 #define GFAR_WOL_MAGIC 0x00000001
562 #define GFAR_WOL_FILER_UCAST 0x00000002
613 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
614 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
615 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
616 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
617 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
618 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
619 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
620 u32 rbyt; /* 0x.69c - Receive Byte Counter */
621 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
622 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
623 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
624 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
625 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
626 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
627 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
628 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
629 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
630 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
631 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
632 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
633 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
634 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
635 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
636 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
637 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
638 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
639 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
640 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
641 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
642 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
643 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
644 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
645 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
646 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
647 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
648 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
650 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
651 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
652 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
653 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
654 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
655 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
656 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
657 u32 car1; /* 0x.730 - Carry Register One */
658 u32 car2; /* 0x.734 - Carry Register Two */
659 u32 cam1; /* 0x.738 - Carry Mask Register One */
660 u32 cam2; /* 0x.73c - Carry Mask Register Two */
696 u32 tsec_id; /* 0x.000 - Controller ID register */
697 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
699 u32 ievent; /* 0x.010 - Interrupt Event Register */
700 u32 imask; /* 0x.014 - Interrupt Mask Register */
701 u32 edis; /* 0x.018 - Error Disabled Register */
702 u32 emapg; /* 0x.01c - Group Error mapping register */
703 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
704 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
705 u32 ptv; /* 0x.028 - Pause Time Value Register */
706 u32 dmactrl; /* 0x.02c - DMA Control Register */
707 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
709 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
713 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
715 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
718 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
720 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
721 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
723 u32 tctrl; /* 0x.100 - Transmit Control Register */
724 u32 tstat; /* 0x.104 - Transmit Status Register */
725 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
726 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
727 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
728 u32 tqueue; /* 0x.114 - Transmit queue control register */
730 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
731 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
733 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
735 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
737 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
739 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
741 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
743 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
745 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
747 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
749 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
751 u32 tbaseh; /* 0x.200 - TxBD base address high */
752 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
754 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
756 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
758 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
760 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
762 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
764 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
766 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
768 u32 rctrl; /* 0x.300 - Receive Control Register */
769 u32 rstat; /* 0x.304 - Receive Status Register */
771 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
772 u32 rqueue; /* 0x.314 - Receive queue control register */
773 u32 rir0; /* 0x.318 - Ring mapping register 0 */
774 u32 rir1; /* 0x.31c - Ring mapping register 1 */
775 u32 rir2; /* 0x.320 - Ring mapping register 2 */
776 u32 rir3; /* 0x.324 - Ring mapping register 3 */
778 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
779 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
780 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
781 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
782 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
784 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
786 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
788 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
790 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
792 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
794 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
796 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
798 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
800 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
802 u32 rbaseh; /* 0x.400 - RxBD base address high */
803 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
805 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
807 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
809 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
811 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
813 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
815 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
817 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
819 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
820 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
821 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
822 u32 hafdup; /* 0x.50c - Half Duplex Register */
823 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
826 u32 ifctrl; /* 0x.538 - Interface control register */
827 u32 ifstat; /* 0x.53c - Interface Status Register */
828 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
829 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
830 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
831 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
832 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
833 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
834 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
835 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
836 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
837 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
838 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
839 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
840 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
841 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
842 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
843 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
844 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
845 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
846 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
847 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
848 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
849 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
850 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
851 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
852 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
853 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
854 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
855 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
856 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
857 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
858 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
859 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
861 struct rmon_mib rmon; /* 0x.680-0x.73c */
862 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
864 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
865 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
866 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
867 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
868 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
869 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
870 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
871 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
873 u32 gaddr0; /* 0x.880 - Group address register 0 */
874 u32 gaddr1; /* 0x.884 - Group address register 1 */
875 u32 gaddr2; /* 0x.888 - Group address register 2 */
876 u32 gaddr3; /* 0x.88c - Group address register 3 */
877 u32 gaddr4; /* 0x.890 - Group address register 4 */
878 u32 gaddr5; /* 0x.894 - Group address register 5 */
879 u32 gaddr6; /* 0x.898 - Group address register 6 */
880 u32 gaddr7; /* 0x.89c - Group address register 7 */
882 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
885 u32 attr; /* 0x.bf8 - Attributes Register */
886 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
887 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
888 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
889 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
890 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
891 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
892 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
893 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
894 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
896 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
898 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
900 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
902 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
904 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
906 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
908 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
910 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
913 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
914 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
915 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
916 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
918 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
919 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
920 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
921 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
922 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
923 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
924 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
925 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
927 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
928 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
929 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
930 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
931 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
932 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
933 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
934 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
939 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
940 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
941 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
942 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
943 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
944 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
945 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
946 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
947 #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
948 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
949 #define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
950 #define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000
951 #define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000
954 #define DEFAULT_MAPPING 0xAA
956 #define DEFAULT_MAPPING 0xFF
959 #define ISRG_RR0 0x80000000
960 #define ISRG_TR0 0x00800000
968 SQ_SG_MODE = 0,
1070 GFAR_TX = 0,
1112 GFAR_ERRATA_74 = 0x01,
1113 GFAR_ERRATA_76 = 0x02,
1114 GFAR_ERRATA_A002 = 0x04,
1115 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */
1238 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_write_filer()
1248 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_read_filer()
1257 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_write_isrg()
1259 u32 isrg = 0; in gfar_write_isrg()
1262 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { in gfar_write_isrg()
1276 isrg = 0; in gfar_write_isrg()
1282 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_is_dma_stopped()
1290 struct gfar __iomem *regs = priv->gfargrp[0].regs; in gfar_is_rx_dma_stopped()
1350 #define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1351 #define RQFCR_PID_L4P_MASK 0xFFFFFF00
1352 #define RQFCR_PID_VID_MASK 0xFFFFF000
1353 #define RQFCR_PID_PORT_MASK 0xFFFF0000
1354 #define RQFCR_PID_MAC_MASK 0xFF000000