101 	return (priv->read_reg(priv, SJA1000_MOD) == 0xFF);  in sja1000_is_absent()
110 		return 0;  in sja1000_probe_chip()
124 	for (i = 0; i < 100; i++) {  in set_reset_mode()
144 	u8 mod_reg_val = 0x00;  in set_normal_mode()
147 	for (i = 0; i < 100; i++) {  in set_normal_mode()
149 		if ((status & MOD_RM) == 0) {  in set_normal_mode()
192 	priv->write_reg(priv, SJA1000_ACCC0, 0x00);  in chipset_init()
193 	priv->write_reg(priv, SJA1000_ACCC1, 0x00);  in chipset_init()
194 	priv->write_reg(priv, SJA1000_ACCC2, 0x00);  in chipset_init()
195 	priv->write_reg(priv, SJA1000_ACCC3, 0x00);  in chipset_init()
197 	priv->write_reg(priv, SJA1000_ACCM0, 0xFF);  in chipset_init()
198 	priv->write_reg(priv, SJA1000_ACCM1, 0xFF);  in chipset_init()
199 	priv->write_reg(priv, SJA1000_ACCM2, 0xFF);  in chipset_init()
200 	priv->write_reg(priv, SJA1000_ACCM3, 0xFF);  in chipset_init()
219 	priv->write_reg(priv, SJA1000_TXERR, 0x0);  in sja1000_start()
220 	priv->write_reg(priv, SJA1000_RXERR, 0x0);  in sja1000_start()
243 	return 0;  in sja1000_set_mode()
252 	btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);  in sja1000_set_bittiming()
253 	btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |  in sja1000_set_bittiming()
254 		(((bt->phase_seg2 - 1) & 0x7) << 4);  in sja1000_set_bittiming()
256 		btr1 |= 0x80;  in sja1000_set_bittiming()
258 	netdev_info(dev, "setting BTR0=0x%02x BTR1=0x%02x\n", btr0, btr1);  in sja1000_set_bittiming()
263 	return 0;  in sja1000_set_bittiming()
274 	return 0;  in sja1000_get_berr_counter()
291 	u8 cmd_reg_val = 0x00;  in sja1000_start_xmit()
309 		priv->write_reg(priv, SJA1000_ID1, (id & 0x1fe00000) >> 21);  in sja1000_start_xmit()
310 		priv->write_reg(priv, SJA1000_ID2, (id & 0x001fe000) >> 13);  in sja1000_start_xmit()
311 		priv->write_reg(priv, SJA1000_ID3, (id & 0x00001fe0) >> 5);  in sja1000_start_xmit()
312 		priv->write_reg(priv, SJA1000_ID4, (id & 0x0000001f) << 3);  in sja1000_start_xmit()
316 		priv->write_reg(priv, SJA1000_ID1, (id & 0x000007f8) >> 3);  in sja1000_start_xmit()
317 		priv->write_reg(priv, SJA1000_ID2, (id & 0x00000007) << 5);  in sja1000_start_xmit()
320 	for (i = 0; i < cf->len; i++)  in sja1000_start_xmit()
323 	can_put_echo_skb(skb, dev, 0, 0);  in sja1000_start_xmit()
371 	can_frame_set_cc_len(cf, fi & 0x0F, priv->can.ctrlmode);  in sja1000_rx()
375 		for (i = 0; i < cf->len; i++)  in sja1000_rx()
398 	can_free_echo_skb(dev, 0, NULL);  in sja1000_reset_interrupt()
416 	int ret = 0;  in sja1000_err()
488 		if ((ecc & ECC_DIR) == 0)  in sja1000_err()
506 		cf->data[0] = alc & 0x1f;  in sja1000_err()
510 		tx_state = txerr >= rxerr ? state : 0;  in sja1000_err()
511 		rx_state = txerr <= rxerr ? state : 0;  in sja1000_err()
530 	irqreturn_t ret = 0;  in sja1000_interrupt()
531 	int n = 0, err;  in sja1000_interrupt()
545 		if (status == 0xFF && sja1000_is_absent(priv))  in sja1000_interrupt()
556 				can_free_echo_skb(dev, 0, NULL);  in sja1000_interrupt()
559 				stats->tx_bytes += can_get_echo_skb(dev, 0, NULL);  in sja1000_interrupt()
570 				if (status == 0xFF && sja1000_is_absent(priv))  in sja1000_interrupt()
627 	return 0;  in sja1000_open()
642 	return 0;  in sja1000_close()
723 	return 0;  in sja1000_init()