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12

/linux-6.12.1/arch/arm/boot/dts/arm/
Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dmediatek,mt7622-ssusbsys.yaml42 reg = <0x1a000000 0x1000>;
Dmediatek,mt2701-hifsys.yaml47 reg = <0x1a000000 0x1000>;
Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/linux-6.12.1/arch/mips/boot/dts/loongson/
Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44 0 0x40000000 0 0x40000000 0 0x40000000
45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
51 ranges = <1 0x0 0x0 0x18000000 0x4000>;
56 reg = <0 0x1fe07000 0 0x422>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dloongson.yaml56 reg = <0x0 0x1a000000 0x0 0x2000000>;
59 ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
60 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
78 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dqca,ar71xx.yaml78 reg = <0x19000000 0x200>;
90 reg = <0x1a000000 0x200>;
106 #size-cells = <0>;
110 reg = <0x10>;
122 #size-cells = <0>;
124 switch_port0: port@0 {
125 reg = <0x0>;
137 reg = <0x1>;
143 reg = <0x2>;
149 reg = <0x3>;
[all …]
/linux-6.12.1/arch/mips/alchemy/devboards/
Ddb1000.c50 return 0; in db1000_board_setup()
57 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
60 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
75 [0] = {
77 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
89 .id = 0,
100 [0] = {
102 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
114 .id = 0,
124 [0] = {
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
Dp2041rdb.dts67 size = <0 0x1000000>;
68 alignment = <0 0x1000000>;
71 size = <0 0x400000>;
72 alignment = <0 0x400000>;
75 size = <0 0x2000000>;
76 alignment = <0 0x2000000>;
81 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
85 ranges = <0x0 0xf 0xf4000000 0x200000>;
89 ranges = <0x0 0xf 0xf4200000 0x200000>;
93 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dp2020ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
[all …]
Dp3041ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
Dp5020ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/linux-6.12.1/arch/mips/boot/dts/qca/
Dar9331.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
34 #clock-cells = <0>;
57 reg = <0x18000000 0x100>;
64 reg = <0x18020000 0x14>;
76 reg = <0x18040000 0x34>;
92 reg = <0x18050000 0x100>;
102 reg = <0x18060010 0x8>;
113 reg = <0x1806001c 0x4>;
[all …]
/linux-6.12.1/arch/mips/loongson64/
Denv.c26 #define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
37 u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
93 smp_group[0] = 0x900000001fe11000; in prom_lefi_init_env()
101 smp_group[0] = 0x900000003ff01000; in prom_lefi_init_env()
102 smp_group[1] = 0x900010003ff01000; in prom_lefi_init_env()
103 smp_group[2] = 0x900020003ff01000; in prom_lefi_init_env()
104 smp_group[3] = 0x900030003ff01000; in prom_lefi_init_env()
105 loongson_chipcfg[0] = 0x900000001fe00180; in prom_lefi_init_env()
106 loongson_chipcfg[1] = 0x900010001fe00180; in prom_lefi_init_env()
107 loongson_chipcfg[2] = 0x900020001fe00180; in prom_lefi_init_env()
[all …]
/linux-6.12.1/arch/arm/mach-versatile/
Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
/linux-6.12.1/arch/mips/sni/
Dpcimt.c31 if (scsiz == 0) { in sni_pcimt_sc_init()
38 cacheconf = 0; in sni_pcimt_sc_init()
44 cacheconf = 0; in sni_pcimt_sc_init()
60 p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300"); in sni_pcimt_detect()
61 if ((csmsr & 0x80) == 0) in sni_pcimt_detect()
63 (csmsr & 0x20) ? "D" : "C"); in sni_pcimt_detect()
64 asic = csmsr & 0x80; in sni_pcimt_detect()
65 asic = (csmsr & 0x08) ? asic : !asic; in sni_pcimt_detect()
80 PORT(0x3f8, 4),
81 PORT(0x2f8, 3),
[all …]
/linux-6.12.1/arch/loongarch/boot/dts/
Dloongson-2k0500.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0>;
29 #clock-cells = <0>;
44 thermal-sensors = <&tsensor 0>;
64 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
65 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
66 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
67 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
68 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
[all …]
/linux-6.12.1/arch/mips/include/asm/ip32/
Dmace.h18 #define MACE_BASE 0x1f000000 /* physical */
43 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
44 #define MACEPCI_ERROR_DEVSEL_FAST 0
45 #define MACEPCI_ERROR_DEVSEL_MED 0x40
46 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
48 #define MACEPCI_ERROR_66MHZ BIT(0)
51 #define MACEPCI_CONTROL_INT_MASK 0xff
61 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
71 unsigned int _pad[0xcf8/4 - 4];
79 #define MACEPCI_LOW_MEMORY 0x1a000000
[all …]

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