mips/sni/pcimt.c

31 	if (scsiz == 0) {  in sni_pcimt_sc_init()
38 		cacheconf = 0;  in sni_pcimt_sc_init()
44 	cacheconf = 0;  in sni_pcimt_sc_init()
60 	p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");  in sni_pcimt_detect()
61 	if ((csmsr & 0x80) == 0)  in sni_pcimt_detect()
63 			     (csmsr & 0x20) ? "D" : "C");  in sni_pcimt_detect()
64 	asic = csmsr & 0x80;  in sni_pcimt_detect()
65 	asic = (csmsr & 0x08) ? asic : !asic;  in sni_pcimt_detect()
80 	PORT(0x3f8, 4),
81 	PORT(0x2f8, 3),
95 		.start = 0x70,
96 		.end   = 0x71,
114 	.start	= 0x00000000UL,
115 	.end	= 0x03bfffffUL,
122 		.start	= 0x00,
123 		.end	= 0x1f,
127 		.start	=  0x40,
128 		.end	= 0x5f,
132 		.start	=  0x60,
133 		.end	= 0x6f,
137 		.start	=  0x80,
138 		.end	= 0x8f,
142 		.start	=  0xc0,
143 		.end	= 0xdf,
147 		.start	=  0xcfc,
148 		.end	= 0xcff,
160 		.start	= 0x1a000000,
161 		.end	= 0x1affffff,
168 	.start	= 0x18000000UL,
169 	.end	= 0x1fbfffffUL,
179 	for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)  in sni_pcimt_resource_init()
182 	for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)  in sni_pcimt_resource_init()
192 	.mem_offset	= 0x00000000UL,
194 	.io_offset	= 0x00000000UL,
246 		if (unlikely(irq < 0))  in pcimt_hwint1()
312 	PCIBIOS_MIN_IO = 0x9000;  in sni_pcimt_init()
329 	return 0;  in snirm_pcimt_setup_devinit()