Home
last modified time | relevance | path

Searched +full:0 +full:x18000 (Results 1 – 25 of 169) sorted by relevance

1234567

/linux-6.12.1/sound/soc/qcom/
Dlpass-sc7280.c114 int chan = 0; in sc7280_lpass_alloc_dma_channel()
193 return 0; in sc7280_lpass_free_dma_channel()
210 for (i = 0; i < drvdata->num_clks; i++) in sc7280_lpass_init()
225 return 0; in sc7280_lpass_init()
233 return 0; in sc7280_lpass_exit()
248 return 0; in sc7280_lpass_dev_suspend()
256 .i2sctrl_reg_base = 0x1000,
257 .i2sctrl_reg_stride = 0x1000,
259 .irq_reg_base = 0x9000,
260 .irq_reg_stride = 0x1000,
[all …]
Dlpass-sc7180.c80 int chan = 0; in sc7180_lpass_alloc_dma_channel()
120 return 0; in sc7180_lpass_free_dma_channel()
137 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
152 return 0; in sc7180_lpass_init()
160 return 0; in sc7180_lpass_exit()
175 return 0; in sc7180_lpass_dev_suspend()
183 .i2sctrl_reg_base = 0x1000,
184 .i2sctrl_reg_stride = 0x1000,
186 .irq_reg_base = 0x9000,
187 .irq_reg_stride = 0x1000,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/ata/
Dfsl-sata.txt13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
15 3 for controller @ 0x1a000
16 4 for controller @ 0x1b000
24 reg = <0x18000 0x1000>;
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dpq3-sata2-0.dtsi2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x18000 ]
37 reg = <0x18000 0x1000>;
39 interrupts = <74 0x2 0 0>;
Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
/linux-6.12.1/drivers/media/common/b2c2/
Dflexcop-sram.c28 return 0; in flexcop_sram_init()
55 return 0; in flexcop_sram_set_dest()
75 #if 0
81 for (i = 0; i < len; i++) {
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
91 if (retries == 0)
94 write_reg_dw(adapter, 0x700, command);
106 for (i = 0; i < len; i++) {
107 command = bank | addr | 0x04008000;
[all …]
/linux-6.12.1/sound/pci/au88x0/
Dau88x0_a3d.h18 #define HRTF_SZ 0x38
19 #define DLINE_SZ 0x28
48 #define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */
49 #define A3D_A_GainCurrent 0x180E0
50 #define A3D_A_GainTarget 0x180E4
51 #define A3D_A_A12Current 0x180E8 /* Atmospheric current. */
52 #define A3D_A_A21Target 0x180EC /* Atmospheric target */
53 #define A3D_A_B01Current 0x180F0 /* Atmospheric current */
54 #define A3D_A_B10Target 0x180F4 /* Atmospheric target */
55 #define A3D_A_B2Current 0x180F8 /* Atmospheric current */
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-390.dtsi19 reg = <0x18000 0x20>;
Darmada-398.dtsi19 reg = <0x18000 0x20>;
24 reg = <0xe0000 0x2000>;
Darmada-395.dtsi19 reg = <0x18000 0x20>;
24 reg = <0xa8000 0x2000>;
32 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
/linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/
Dccf.txt42 reg = <0x18000 0x1000>;
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv04.c51 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
59 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32()
78 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire()
137 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv04_instobj_new()
149 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32()
155 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
197 return 0; in nv04_instmem_suspend()
210 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit()
214 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit()
215 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit()
[all …]
Dnv40.c136 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv40_instobj_new()
168 vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8); in nv40_instmem_oneinit()
169 if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; in nv40_instmem_oneinit()
170 else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; in nv40_instmem_oneinit()
171 else if (nv44_gr_class(device)) imem->base.reserved = 0x4980 * vs; in nv40_instmem_oneinit()
172 else imem->base.reserved = 0x4a40 * vs; in nv40_instmem_oneinit()
179 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv40_instmem_oneinit()
183 /* 0x00000-0x10000: reserve for probable vbios image */ in nv40_instmem_oneinit()
184 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv40_instmem_oneinit()
189 /* 0x10000-0x18000: reserve for RAMHT */ in nv40_instmem_oneinit()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Djpeg_v4_0_3.h27 #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
28 #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d
29 #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e
30 #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f
31 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab
32 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac
33 #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4
34 #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6
35 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6
36 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7
[all …]
Djpeg_v2_0.h27 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
28 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029
29 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x402a
30 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x402b
31 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ea
32 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40eb
33 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40cf
34 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40d1
35 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40e8
36 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40e9
[all …]
/linux-6.12.1/drivers/dma/amd/qdma/
Dqdma-comm-regs.c12 [QDMA_REGO_CTXT_DATA] = QDMA_REGO(0x804, 8),
13 [QDMA_REGO_CTXT_CMD] = QDMA_REGO(0x844, 1),
14 [QDMA_REGO_CTXT_MASK] = QDMA_REGO(0x824, 8),
15 [QDMA_REGO_MM_H2C_CTRL] = QDMA_REGO(0x1004, 1),
16 [QDMA_REGO_MM_C2H_CTRL] = QDMA_REGO(0x1204, 1),
17 [QDMA_REGO_QUEUE_COUNT] = QDMA_REGO(0x120, 1),
18 [QDMA_REGO_RING_SIZE] = QDMA_REGO(0x204, 1),
19 [QDMA_REGO_H2C_PIDX] = QDMA_REGO(0x18004, 1),
20 [QDMA_REGO_C2H_PIDX] = QDMA_REGO(0x18008, 1),
21 [QDMA_REGO_INTR_CIDX] = QDMA_REGO(0x18000, 1),
[all …]
/linux-6.12.1/drivers/gpu/drm/imx/dcss/
Ddcss-drv.c40 int err = 0; in dcss_drv_platform_probe()
46 remote = of_graph_get_remote_node(dev->of_node, 0, 0); in dcss_drv_platform_probe()
71 return 0; in dcss_drv_platform_probe()
97 .blkctl_ofs = 0x2F000,
98 .ctxld_ofs = 0x23000,
99 .dtg_ofs = 0x20000,
100 .scaler_ofs = 0x1C000,
101 .ss_ofs = 0x1B000,
102 .dpr_ofs = 0x18000,
/linux-6.12.1/drivers/net/ethernet/intel/fm10k/
Dfm10k_mbx.h14 #define FM10K_MBMEM(_n) ((_n) + 0x18000)
15 #define FM10K_MBMEM_VF(_n, _m) (((_n) * 0x10) + (_m) + 0x18000)
16 #define FM10K_MBMEM_SM(_n) ((_n) + 0x18400)
17 #define FM10K_MBMEM_PF(_n) ((_n) + 0x18600)
19 #define FM10K_MBMEM_PF_XOR (FM10K_MBMEM_SM(0) ^ FM10K_MBMEM_PF(0))
20 #define FM10K_MBX(_n) ((_n) + 0x18800)
21 #define FM10K_MBX_REQ 0x00000002
22 #define FM10K_MBX_ACK 0x00000004
23 #define FM10K_MBX_REQ_INTERRUPT 0x00000008
24 #define FM10K_MBX_ACK_INTERRUPT 0x00000010
[all …]
/linux-6.12.1/arch/arc/boot/dts/
Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/cfg/
D8000.c20 #define IWL8000_NVM_VERSION 0x0a1d
23 #define IWL8260_DCCM_OFFSET 0x800000
24 #define IWL8260_DCCM_LEN 0x18000
25 #define IWL8260_DCCM2_OFFSET 0x880000
26 #define IWL8260_DCCM2_LEN 0x8000
27 #define IWL8260_SMEM_OFFSET 0x400000
28 #define IWL8260_SMEM_LEN 0x68000
97 .min_umac_error_event_table = 0x800000
/linux-6.12.1/drivers/media/dvb-frontends/
Dbsbe1.h12 0x01, 0x15, /* XTAL = 4MHz, VCO = 352 MHz */
13 0x02, 0x30, /* MCLK = 88 MHz */
14 0x03, 0x00, /* ACR output 0 */
15 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
16 0x05, 0x05, /* I2CT = 0, SCLT = 1, SDAT = 1 */
17 0x06, 0x00, /* DAC output 0 */
18 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
19 0x09, 0x00, /* FIFO */
20 0x0c, 0x51, /* OP1/OP0 normal, val = 1 (LNB power on) */
21 0x0d, 0x82, /* DC offset compensation = on, beta_agc1 = 2 */
[all …]
/linux-6.12.1/drivers/media/pci/intel/ipu6/
Dipu6-platform-isys-csi2-reg.h9 #define CSI_REG_BASE 0x220000
10 #define CSI_REG_PORT_BASE(id) (CSI_REG_BASE + (id) * 0x1000)
13 #define CSI_REG_PORT_GPREG_SRST 0x0
14 #define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST 0x4
15 #define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL 0x8
24 #define CSI_PORT_REG_BASE_IRQ_CSI 0x80
25 #define CSI_PORT_REG_BASE_IRQ_CSI_SYNC 0xA0
26 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7 0xC0
27 #define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15 0xE0
29 #define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET 0x0
[all …]

1234567