Lines Matching +full:0 +full:x18000
114 int chan = 0; in sc7280_lpass_alloc_dma_channel()
193 return 0; in sc7280_lpass_free_dma_channel()
210 for (i = 0; i < drvdata->num_clks; i++) in sc7280_lpass_init()
225 return 0; in sc7280_lpass_init()
233 return 0; in sc7280_lpass_exit()
248 return 0; in sc7280_lpass_dev_suspend()
256 .i2sctrl_reg_base = 0x1000,
257 .i2sctrl_reg_stride = 0x1000,
259 .irq_reg_base = 0x9000,
260 .irq_reg_stride = 0x1000,
262 .rdma_reg_base = 0xC000,
263 .rdma_reg_stride = 0x1000,
265 .rxtx_rdma_reg_base = 0xC000,
266 .rxtx_rdma_reg_stride = 0x1000,
268 .hdmi_rdma_reg_base = 0x64000,
269 .hdmi_rdma_reg_stride = 0x1000,
272 .wrdma_reg_base = 0x18000,
273 .wrdma_reg_stride = 0x1000,
276 .rxtx_irq_reg_base = 0x9000,
277 .rxtx_irq_reg_stride = 0x1000,
279 .rxtx_wrdma_reg_base = 0x18000,
280 .rxtx_wrdma_reg_stride = 0x1000,
283 .va_wrdma_reg_base = 0x18000,
284 .va_wrdma_reg_stride = 0x1000,
287 .va_irq_reg_base = 0x9000,
288 .va_irq_reg_stride = 0x1000,
291 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
292 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
293 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
294 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
295 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
296 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
297 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
298 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
299 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
301 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
302 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
303 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
304 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
305 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
306 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
308 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
309 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
310 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
311 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
312 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
313 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
315 .rxtx_rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 7, 0x1000),
316 .rxtx_rdma_fifowm = REG_FIELD_ID(0xC000, 1, 11, 7, 0x1000),
317 .rxtx_rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 7, 0x1000),
318 .rxtx_rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 7, 0x1000),
319 .rxtx_rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 7, 0x1000),
320 .rxtx_rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 7, 0x1000),
322 .rxtx_rdma_codec_ch = REG_FIELD_ID(0xC050, 0, 7, 7, 0x1000),
323 .rxtx_rdma_codec_intf = REG_FIELD_ID(0xC050, 16, 19, 7, 0x1000),
324 .rxtx_rdma_codec_fs_delay = REG_FIELD_ID(0xC050, 21, 24, 7, 0x1000),
325 .rxtx_rdma_codec_fs_sel = REG_FIELD_ID(0xC050, 25, 27, 7, 0x1000),
326 .rxtx_rdma_codec_pack = REG_FIELD_ID(0xC050, 29, 29, 5, 0x1000),
327 .rxtx_rdma_codec_enable = REG_FIELD_ID(0xC050, 30, 30, 7, 0x1000),
329 .rxtx_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
330 .rxtx_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
331 .rxtx_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
332 .rxtx_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
333 .rxtx_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
334 .rxtx_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
336 .rxtx_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
337 .rxtx_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
338 .rxtx_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
339 .rxtx_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
340 .rxtx_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
341 .rxtx_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
343 .va_wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 5, 0x1000),
344 .va_wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 11, 5, 0x1000),
345 .va_wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 5, 0x1000),
346 .va_wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 5, 0x1000),
347 .va_wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 5, 0x1000),
348 .va_wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 5, 0x1000),
350 .va_wrdma_codec_ch = REG_FIELD_ID(0x18050, 0, 7, 5, 0x1000),
351 .va_wrdma_codec_intf = REG_FIELD_ID(0x18050, 16, 19, 5, 0x1000),
352 .va_wrdma_codec_fs_delay = REG_FIELD_ID(0x18050, 21, 24, 5, 0x1000),
353 .va_wrdma_codec_fs_sel = REG_FIELD_ID(0x18050, 25, 27, 5, 0x1000),
354 .va_wrdma_codec_pack = REG_FIELD_ID(0x18050, 29, 29, 5, 0x1000),
355 .va_wrdma_codec_enable = REG_FIELD_ID(0x18050, 30, 30, 5, 0x1000),
357 .hdmi_tx_ctl_addr = 0x1000,
358 .hdmi_legacy_addr = 0x1008,
359 .hdmi_vbit_addr = 0x610c0,
360 .hdmi_ch_lsb_addr = 0x61048,
361 .hdmi_ch_msb_addr = 0x6104c,
362 .ch_stride = 0x8,
363 .hdmi_parity_addr = 0x61034,
364 .hdmi_dmactl_addr = 0x61038,
365 .hdmi_dma_stride = 0x4,
366 .hdmi_DP_addr = 0x610c8,
367 .hdmi_sstream_addr = 0x6101c,
368 .hdmi_irq_reg_base = 0x63000,
371 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
372 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
373 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
374 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
375 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
376 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
377 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
378 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
380 .sstream_en = REG_FIELD(0x6101c, 0, 0),
381 .dma_sel = REG_FIELD(0x6101c, 1, 2),
382 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
383 .layout = REG_FIELD(0x6101c, 4, 4),
384 .layout_sp = REG_FIELD(0x6101c, 5, 8),
385 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
386 .dp_audio = REG_FIELD(0x6101c, 11, 11),
387 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
388 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
390 .mute = REG_FIELD(0x610c8, 0, 0),
391 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
392 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
393 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
394 .frequency = REG_FIELD(0x610c8, 16, 21),
395 .mst_index = REG_FIELD(0x610c8, 28, 29),
396 .dptx_index = REG_FIELD(0x610c8, 30, 31),
398 .soft_reset = REG_FIELD(0x1000, 31, 31),
399 .force_reset = REG_FIELD(0x1000, 30, 30),
401 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
402 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
403 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
404 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
406 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
407 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
409 .legacy_en = REG_FIELD(0x1008, 0, 0),
410 .calc_en = REG_FIELD(0x61034, 0, 0),
411 .lsb_bits = REG_FIELD(0x61048, 0, 31),
412 .msb_bits = REG_FIELD(0x6104c, 0, 31),