Lines Matching +full:0 +full:x18000
27 #define regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET 0x1bfff
28 #define regUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x404d
29 #define regUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET 0x404e
30 #define regUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET 0x404f
31 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40ab
32 #define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40ac
33 #define regUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET 0x40a4
34 #define regUVD_LMI_JPEG_VMID_INTERNAL_OFFSET 0x40a6
35 #define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x40b6
36 #define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x40b7
37 #define regUVD_JRBC_IB_SIZE_INTERNAL_OFFSET 0x4082
38 #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET 0x42d4
39 #define regUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x42d5
40 #define regUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET 0x4085
41 #define regUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET 0x4084
42 #define regUVD_JRBC_STATUS_INTERNAL_OFFSET 0x4089
43 #define regUVD_JPEG_PITCH_INTERNAL_OFFSET 0x4043
44 #define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094
45 #define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe
47 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000