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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dstarfive,jh7100-clkgen.yaml52 reg = <0x11800000 0x10000>;
/linux-6.12.1/arch/arm/mach-davinci/
Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dti,davinci-rproc.txt57 reg = <0xc3000000 0x1000000>;
66 reg = <0x11800000 0x40000>,
67 <0x11e00000 0x8000>,
68 <0x11f00000 0x8000>,
69 <0x01c14044 0x4>,
70 <0x01c14174 0x8>;
/linux-6.12.1/arch/sh/boards/mach-se/7722/
Dirq.c20 #define IRQ01_BASE_ADDR 0x11800000
21 #define IRQ01_MODE_REG 0
56 for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { in se7722_domain_init()
59 if (unlikely(irq == 0)) { in se7722_domain_init()
72 irq_base = irq_linear_revmap(se7722_irq_domain, 0); in se7722_gc_init()
87 IRQ_NOREQUEST | IRQ_NOPROBE, 0); in se7722_gc_init()
110 iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG); in init_se7722_IRQ()
112 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */ in init_se7722_IRQ()
/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/davinci/
Dpsc.txt34 reg = <0x10000 0x1000>;
45 reg = <0x227000 0x1000>;
55 reg = <0x11800000 0x40000>,
56 <0x11e00000 0x8000>,
57 <0x11f00000 0x8000>,
58 <0x01c14044 0x4>,
59 <0x01c14174 0x8>;
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dsamsung,exynos4210-fimc.yaml91 0 - scaler input horizontal size
98 default: 0x11
101 rotator. Bits 4 and 0 correspond to input and output rotator
134 reg = <0x11800000 0x1000>;
151 assigned-clock-rates = <0>, <176000000>;
/linux-6.12.1/arch/sh/boards/mach-se/7343/
Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/keystone/
Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
Dkeystone-k2l.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
49 reg = <0x02348400 0x100>;
59 reg = <0x02348800 0x100>;
66 reg = <0x02348000 0x100>;
110 reg = <0x02620690 0xc>;
112 #size-cells = <0>;
116 pinctrl-single,function-mask = <0x1>;
122 0x0 0x0 0xc0
[all …]
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi18 #size-cells = <0>;
20 U74_0: cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
121 clock-frequency = <0>;
126 #clock-cells = <0>;
129 clock-frequency = <0>;
134 #clock-cells = <0>;
137 clock-frequency = <0>;
142 #clock-cells = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr9a09g057.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 reg = <0>;
37 reg = <0x100>;
45 reg = <0x200>;
53 reg = <0x300>;
59 L3_CA55: cache-controller-0 {
62 cache-size = <0x100000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/samsung/
Dexynos4x12.dtsi70 #interconnect-cells = <0>;
80 #interconnect-cells = <0>;
120 #interconnect-cells = <0>;
211 reg = <0x11400000 0x1000>;
217 reg = <0x11000000 0x1000>;
229 reg = <0x03860000 0x1000>;
231 interrupts = <10 0>;
236 reg = <0x106e0000 0x1000>;
242 reg = <0x02020000 0x40000>;
245 ranges = <0 0x02020000 0x40000>;
[all …]
Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]
Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/linux-6.12.1/arch/hexagon/kernel/
Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
102 reg = <0x1>;
108 reg = <0x2>;
114 reg = <0x3>;
120 reg = <0x100>;
128 reg = <0x101>;
134 reg = <0x102>;
[all …]
Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]
/linux-6.12.1/arch/parisc/mm/
Dinit.c61 .start = 0,
62 .end = 0x9ff,
92 if (memcmp(cp, "mem=", 4) == 0) { in mem_limit_func()
110 #define MAX_GAP (0x40000000UL >> PAGE_SHIFT)
132 for (j = i; j > 0; j--) { in setup_bootmem()
166 for (i = 0; i < npmem_ranges; i++) { in setup_bootmem()
173 pr_info("%2d) Start 0x%016lx End 0x%016lx Size %6ld MB\n", in setup_bootmem()
197 mem_max = 0; in setup_bootmem()
198 for (i = 0; i < npmem_ranges; i++) { in setup_bootmem()
225 npmem_holes = 0; in setup_bootmem()
[all …]
/linux-6.12.1/arch/arm/boot/dts/ti/davinci/
Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/linux-6.12.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main.c55 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
56 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
57 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
58 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
59 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
60 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
61 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
62 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
63 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
64 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-au1x00/
Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynos850.c37 /* Register Offset definitions for CMU_TOP (0x120e0000) */
38 #define PLL_LOCKTIME_PLL_MMC 0x0000
39 #define PLL_LOCKTIME_PLL_SHARED0 0x0004
40 #define PLL_LOCKTIME_PLL_SHARED1 0x0008
41 #define PLL_CON0_PLL_MMC 0x0100
42 #define PLL_CON3_PLL_MMC 0x010c
43 #define PLL_CON0_PLL_SHARED0 0x0140
44 #define PLL_CON3_PLL_SHARED0 0x014c
45 #define PLL_CON0_PLL_SHARED1 0x0180
46 #define PLL_CON3_PLL_SHARED1 0x018c
[all …]