dts/renesas/r9a09g057.dtsi

18 		#clock-cells = <0>;
20 		clock-frequency = <0>;
25 		#size-cells = <0>;
27 		cpu0: cpu@0 {
29 			reg = <0>;
37 			reg = <0x100>;
45 			reg = <0x200>;
53 			reg = <0x300>;
59 		L3_CA55: cache-controller-0 {
62 			cache-size = <0x100000>;
74 		#clock-cells = <0>;
76 		clock-frequency = <0>;
81 		#clock-cells = <0>;
83 		clock-frequency = <0>;
95 			reg = <0 0x10410000 0 0x10000>;
99 			gpio-ranges = <&pinctrl 0 0 96>;
103 			resets = <&cpg 0xa5>, <&cpg 0xa6>;
108 			reg = <0 0x10420000 0 0x10000>;
113 			#power-domain-cells = <0>;
118 			reg = <0 0x10430000 0 0x10000>;
120 			resets = <&cpg 0x30>;
126 			reg = <0x0 0x11800000 0x0 0x1000>;
128 			clocks = <&cpg CPG_MOD 0x43>;
129 			resets = <&cpg 0x6d>;
136 			reg = <0x0 0x11801000 0x0 0x1000>;
138 			clocks = <&cpg CPG_MOD 0x44>;
139 			resets = <&cpg 0x6e>;
146 			reg = <0x0 0x14000000 0x0 0x1000>;
148 			clocks = <&cpg CPG_MOD 0x45>;
149 			resets = <&cpg 0x6f>;
156 			reg = <0x0 0x14001000 0x0 0x1000>;
158 			clocks = <&cpg CPG_MOD 0x46>;
159 			resets = <&cpg 0x70>;
166 			reg = <0x0 0x12c00000 0x0 0x1000>;
168 			clocks = <&cpg CPG_MOD 0x47>;
169 			resets = <&cpg 0x71>;
176 			reg = <0x0 0x12c01000 0x0 0x1000>;
178 			clocks = <&cpg CPG_MOD 0x48>;
179 			resets = <&cpg 0x72>;
186 			reg = <0x0 0x12c02000 0x0 0x1000>;
188 			clocks = <&cpg CPG_MOD 0x49>;
189 			resets = <&cpg 0x73>;
196 			reg = <0x0 0x12c03000 0x0 0x1000>;
198 			clocks = <&cpg CPG_MOD 0x4a>;
199 			resets = <&cpg 0x74>;
206 			reg = <0 0x11c00400 0 0x400>;
207 			clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>;
209 			resets = <&cpg 0x75>;
216 			reg = <0 0x14400000 0 0x400>;
217 			clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
219 			resets = <&cpg 0x76>;
226 			reg = <0 0x13000000 0 0x400>;
227 			clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
229 			resets = <&cpg 0x77>;
236 			reg = <0 0x13000400 0 0x400>;
237 			clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
239 			resets = <&cpg 0x78>;
246 			reg = <0 0x11c01400 0 0x400>;
258 			clocks = <&cpg CPG_MOD 0x8f>;
261 			resets = <&cpg 0x95>;
267 			reg = <0 0x14400400 0 0x400>;
278 			clocks = <&cpg CPG_MOD 0x94>;
279 			resets = <&cpg 0x98>;
282 			#size-cells = <0>;
288 			reg = <0 0x14400800 0 0x400>;
299 			clocks = <&cpg CPG_MOD 0x95>;
300 			resets = <&cpg 0x99>;
303 			#size-cells = <0>;
309 			reg = <0 0x14400c00 0 0x400>;
320 			clocks = <&cpg CPG_MOD 0x96>;
321 			resets = <&cpg 0x9a>;
324 			#size-cells = <0>;
330 			reg = <0 0x14401000 0 0x400>;
341 			clocks = <&cpg CPG_MOD 0x97>;
342 			resets = <&cpg 0x9b>;
345 			#size-cells = <0>;
351 			reg = <0 0x14401400 0 0x400>;
362 			clocks = <&cpg CPG_MOD 0x98>;
363 			resets = <&cpg 0x9c>;
366 			#size-cells = <0>;
372 			reg = <0 0x14401800 0 0x400>;
383 			clocks = <&cpg CPG_MOD 0x99>;
384 			resets = <&cpg 0x9d>;
387 			#size-cells = <0>;
393 			reg = <0 0x14401c00 0 0x400>;
404 			clocks = <&cpg CPG_MOD 0x9a>;
405 			resets = <&cpg 0x9e>;
408 			#size-cells = <0>;
414 			reg = <0 0x14402000 0 0x400>;
425 			clocks = <&cpg CPG_MOD 0x9b>;
426 			resets = <&cpg 0x9f>;
429 			#size-cells = <0>;
435 			reg = <0 0x11c01000 0 0x400>;
446 			clocks = <&cpg CPG_MOD 0x93>;
447 			resets = <&cpg 0xa0>;
450 			#size-cells = <0>;
456 			reg = <0x0 0x14900000 0 0x20000>,
457 			      <0x0 0x14940000 0 0x80000>;
459 			#address-cells = <0>;
466 			reg = <0x0 0x15c00000 0 0x10000>;
469 			clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
470 				 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
472 			resets = <&cpg 0xa7>;
479 			reg = <0x0 0x15c10000 0 0x10000>;
482 			clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
483 				 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
485 			resets = <&cpg 0xa8>;
492 			reg = <0x0 0x15c20000 0 0x10000>;
495 			clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
496 				 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
498 			resets = <&cpg 0xa9>;