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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-usb-phy.yaml20 const: 0
45 reg = <0x10200000 0x10000>;
49 #phy-cells = <0>;
/linux-6.12.1/arch/mips/boot/dts/xilfpga/
Dnexys4ddr.dts19 reg = <0x0 0x08000000>;
23 #address-cells = <0>;
33 reg = <0x10200000 0x10000>;
34 xlnx,kind-of-intr = <0x0>;
35 xlnx,num-intr-inputs = <0x6>;
45 reg = <0x10600000 0x10000>;
46 xlnx,all-inputs = <0x0>;
47 xlnx,dout-default = <0x0>;
48 xlnx,gpio-width = <0x16>;
49 xlnx,interrupt-present = <0x0>;
[all …]
/linux-6.12.1/drivers/staging/rtl8712/
Drtl8712_spec.h17 #define RTL8712_IOBASE_TXPKT 0x10200000 /*IOBASE_TXPKT*/
18 #define RTL8712_IOBASE_RXPKT 0x10210000 /*IOBASE_RXPKT*/
19 #define RTL8712_IOBASE_RXCMD 0x10220000 /*IOBASE_RXCMD*/
20 #define RTL8712_IOBASE_TXSTATUS 0x10230000 /*IOBASE_TXSTATUS*/
21 #define RTL8712_IOBASE_RXSTATUS 0x10240000 /*IOBASE_RXSTATUS*/
22 #define RTL8712_IOBASE_IOREG 0x10250000 /*IOBASE_IOREG ADDR*/
23 #define RTL8712_IOBASE_SCHEDULER 0x10260000 /*IOBASE_SCHEDULE*/
25 #define RTL8712_IOBASE_TRXDMA 0x10270000 /*IOBASE_TRXDMA*/
26 #define RTL8712_IOBASE_TXLLT 0x10280000 /*IOBASE_TXLLT*/
27 #define RTL8712_IOBASE_WMAC 0x10290000 /*IOBASE_WMAC*/
[all …]
/linux-6.12.1/arch/arm/boot/dts/samsung/
Dexynos5260.dtsi35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
128 reg = <0x10200000 0x10000>;
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-au1x00/
Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]
/linux-6.12.1/arch/arm/boot/dts/arm/
Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
82 #clock-cells = <0>;
84 clock-frequency = <0>;
89 reg = <0x30000000 0x4000000>;
98 reg = <0x38000000 0x800000>;
113 reg = <0x3c000000 0x4000000>;
121 reg = <0x3a000000 0x10000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/rockchip/
Drk3036.dtsi37 #size-cells = <0>;
43 reg = <0xf00>;
56 reg = <0xf01>;
87 #clock-cells = <0>;
92 reg = <0x10080000 0x2000>;
95 ranges = <0 0x10080000 0x2000>;
97 smp-sram@0 {
99 reg = <0x00 0x10>;
105 reg = <0x10090000 0x10000>;
125 reg = <0x10108000 0x800>;
[all …]
Drk3128.dtsi44 #size-cells = <0>;
50 reg = <0xf00>;
61 reg = <0xf01>;
69 reg = <0xf02>;
77 reg = <0xf03>;
83 cpu_opp_table: opp-table-0 {
159 #clock-cells = <0>;
164 reg = <0x10080000 0x2000>;
167 ranges = <0 0x10080000 0x2000>;
169 smp-sram@0 {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8365.dtsi24 #size-cells = <0>;
26 cluster0_opp: opp-table-0 {
128 cpu0: cpu@0 {
131 reg = <0x0>;
135 i-cache-size = <0x8000>;
138 d-cache-size = <0x8000>;
151 reg = <0x1>;
155 i-cache-size = <0x8000>;
158 d-cache-size = <0x8000>;
171 reg = <0x2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/tesla/
Dfsd.dtsi39 #size-cells = <0>;
88 /* Cluster 0 */
89 cpucl0_0: cpu@0 {
92 reg = <0x0 0x000>;
96 i-cache-size = <0xc000>;
99 d-cache-size = <0x8000>;
108 reg = <0x0 0x001>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
124 reg = <0x0 0x002>;
[all …]
/linux-6.12.1/arch/mips/alchemy/common/
Ddbdma.c68 { AU1550_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
69 { AU1550_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
70 { AU1550_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
71 { AU1550_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
74 { AU1550_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
75 { AU1550_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
76 { AU1550_DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
77 { AU1550_DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
80 { AU1550_DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
81 { AU1550_DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
[all …]
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-exynosautov9.c33 /* Register Offset definitions for CMU_TOP (0x1b240000) */
34 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
35 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
36 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
37 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
38 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
39 #define PLL_CON0_PLL_SHARED0 0x0100
40 #define PLL_CON3_PLL_SHARED0 0x010c
41 #define PLL_CON0_PLL_SHARED1 0x0140
42 #define PLL_CON3_PLL_SHARED1 0x014c
[all …]
/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/linux-6.12.1/lib/crypto/
Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dar9003_eeprom.c31 #define EXT_ADDITIVE (0x8000)
49 .macAddr = {0, 2, 3, 4, 5, 6},
50 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
51 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
53 .regDmn = { LE16(0), LE16(0x1f) },
54 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
59 .rfSilent = 0,
60 .blueToothOptions = 0,
61 .deviceCap = 0,
64 .params_for_tuning_caps = {0, 0},
[all …]