Lines Matching +full:0 +full:x10200000
21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
101 reg = <0x0 0x4ab00000 0x0 0x100000>;
108 reg = <0x0 0x4ac00000 0x0 0x400000>;
116 qcom,dload-mode = <&tcsr 0x6100>;
120 soc: soc@0 {
123 ranges = <0 0 0 0xffffffff>;
128 reg = <0x00058000 0x1000>;
139 #clock-cells = <0>;
140 #phy-cells = <0>;
152 reg = <0x00059000 0x180>;
153 #phy-cells = <0>;
165 reg = <0x00078000 0x1000>;
176 #clock-cells = <0>;
177 #phy-cells = <0>;
189 reg = <0x00079000 0x180>;
190 #phy-cells = <0>;
202 reg = <0x00084000 0x1000>;
212 #clock-cells = <0>;
214 #phy-cells = <0>;
225 reg = <0x0008e000 0x1000>;
235 #clock-cells = <0>;
237 #phy-cells = <0>;
248 reg = <0x00090000 0x64>;
250 #size-cells = <0>;
262 reg = <0x000a4000 0x2000>;
269 reg = <0x000e3000 0x1000>;
277 reg = <0x4a9000 0x1000>, /* TM */
278 <0x4a8000 0x1000>; /* SROT */
287 reg = <0x00704000 0x20000>;
299 reg = <0x0073a000 0x6000>;
311 reg = <0x01000000 0x300000>;
314 gpio-ranges = <&tlmm 0 0 70>;
333 i2c_0_pins: i2c-0-state {
340 spi_0_pins: spi-0-state {
368 reg = <0x01800000 0x80000>;
384 reg = <0x01905000 0x20000>;
390 reg = <0x01937000 0x21000>;
395 reg = <0x0200f000 0x001000>,
396 <0x02400000 0x800000>,
397 <0x02c00000 0x800000>,
398 <0x03800000 0x200000>,
399 <0x0200a000 0x000700>;
403 qcom,ee = <0>;
404 qcom,channel = <0>;
406 #size-cells = <0>;
413 reg = <0x7824900 0x500>, <0x7824000 0x800>;
436 reg = <0x07884000 0x2b000>;
441 qcom,ee = <0>;
446 reg = <0x078af000 0x200>;
456 reg = <0x078b1000 0x200>;
464 pinctrl-0 = <&hsuart_pins>;
471 reg = <0x078b3000 0x200>;
476 pinctrl-0 = <&serial_4_pins>;
483 reg = <0x078b4000 0x200>;
488 pinctrl-0 = <&serial_5_pins>;
496 #size-cells = <0>;
497 reg = <0x078b5000 0x600>;
504 pinctrl-0 = <&spi_0_pins>;
512 #size-cells = <0>;
513 reg = <0x078b6000 0x600>;
521 pinctrl-0 = <&i2c_0_pins>;
529 #size-cells = <0>;
530 reg = <0x078b7000 0x600>;
544 #size-cells = <0>;
545 reg = <0x78b8000 0x600>;
558 #size-cells = <0>;
559 reg = <0x78b9000 0x600>;
573 #size-cells = <0>;
574 reg = <0x78b9000 0x600>;
587 #size-cells = <0>;
588 reg = <0x078ba000 0x600>;
601 reg = <0x07984000 0x1a000>;
606 qcom,ee = <0>;
612 reg = <0x079b0000 0x10000>;
614 #size-cells = <0>;
619 dmas = <&qpic_bam 0>,
623 pinctrl-0 = <&qpic_pins>;
630 reg = <0x08af8800 0x400>;
665 reg = <0x8a00000 0xcd00>;
671 snps,hird-threshold = /bits/ 8 <0x0>;
680 reg = <0x08cf8800 0x400>;
715 reg = <0x8c00000 0xcd00>;
721 snps,hird-threshold = /bits/ 8 <0x0>;
734 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
735 ranges = <0 0xb00a000 0xffd>;
737 v2m@0 {
740 reg = <0x0 0xffd>;
746 reg = <0xb017000 0x1000>;
755 reg = <0x0b111000 0x1000>;
765 reg = <0x0b116000 0x40>;
766 #clock-cells = <0>;
776 reg = <0x0b120000 0x1000>;
779 frame-number = <0>;
782 reg = <0x0b121000 0x1000>,
783 <0x0b122000 0x1000>;
789 reg = <0x0b123000 0x1000>;
796 reg = <0x0b124000 0x1000>;
803 reg = <0x0b125000 0x1000>;
810 reg = <0x0b126000 0x1000>;
817 reg = <0x0b127000 0x1000>;
824 reg = <0x0b128000 0x1000>;
831 reg = <0x10000000 0xf1d>,
832 <0x10000f20 0xa8>,
833 <0x00088000 0x2000>,
834 <0x10100000 0x1000>;
838 bus-range = <0x00 0xff>;
847 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
848 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
853 interrupt-map-mask = <0 0 0 0x7>;
854 interrupt-map = <0 0 0 1 &intc 0 0 142
856 <0 0 0 2 &intc 0 0 143
858 <0 0 0 3 &intc 0 0 144
860 <0 0 0 4 &intc 0 0 145
889 pcie@0 {
891 reg = <0x0 0x0 0x0 0x0 0x0>;
892 bus-range = <0x01 0xff>;
902 reg = <0x20000000 0xf1d>,
903 <0x20000f20 0xa8>,
904 <0x20001000 0x1000>,
905 <0x00080000 0x4000>,
906 <0x20100000 0x1000>;
909 linux,pci-domain = <0>;
910 bus-range = <0x00 0xff>;
919 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
920 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
925 interrupt-map-mask = <0 0 0 0x7>;
926 interrupt-map = <0 0 0 1 &intc 0 0 75
928 <0 0 0 2 &intc 0 0 78
930 <0 0 0 3 &intc 0 0 79
932 <0 0 0 4 &intc 0 0 83
964 pcie@0 {
966 reg = <0x0 0x0 0x0 0x0 0x0>;
967 bus-range = <0x01 0xff>;
1005 nss-0-crit {