Lines Matching +full:0 +full:x10200000
33 /* Register Offset definitions for CMU_TOP (0x1b240000) */
34 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
35 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
36 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
37 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
38 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
39 #define PLL_CON0_PLL_SHARED0 0x0100
40 #define PLL_CON3_PLL_SHARED0 0x010c
41 #define PLL_CON0_PLL_SHARED1 0x0140
42 #define PLL_CON3_PLL_SHARED1 0x014c
43 #define PLL_CON0_PLL_SHARED2 0x0180
44 #define PLL_CON3_PLL_SHARED2 0x018c
45 #define PLL_CON0_PLL_SHARED3 0x01c0
46 #define PLL_CON3_PLL_SHARED3 0x01cc
47 #define PLL_CON0_PLL_SHARED4 0x0200
48 #define PLL_CON3_PLL_SHARED4 0x020c
51 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
52 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
53 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
54 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
55 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
56 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
57 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
58 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
59 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
63 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
64 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
65 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
66 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
67 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
68 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
69 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
70 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
71 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
72 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
73 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
74 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
75 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
76 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
77 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
78 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
79 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
80 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
81 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
82 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
83 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
84 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
85 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
86 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
87 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
88 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
89 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
90 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
91 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
92 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
93 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
96 #define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
97 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
98 #define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
99 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
100 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
101 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
102 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
103 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
104 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
105 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
106 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
107 #define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
108 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
109 #define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
110 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
111 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
112 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
113 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
114 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
115 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
116 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
117 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
118 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
119 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
120 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
121 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
122 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
123 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
124 #define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
125 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
126 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
127 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
128 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
129 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
130 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
131 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
132 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
133 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
134 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
136 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
137 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
138 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
139 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
140 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
141 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
142 #define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
143 #define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
144 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
145 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
148 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
149 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
150 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
151 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
152 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
153 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
154 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
155 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
156 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
157 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
158 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
159 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
160 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
161 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
162 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
163 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
164 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
165 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
166 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
167 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
168 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
169 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
170 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
171 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
172 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
173 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
174 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
175 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
176 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
177 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
178 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
179 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
180 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
181 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
182 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
183 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
184 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
185 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
186 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
187 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
188 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
189 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
190 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
191 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
192 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
193 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
194 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
456 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
458 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
462 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
466 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
470 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
472 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
476 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
480 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
484 mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
489 0, 2),
492 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
497 0, 2),
500 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
504 mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
506 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
510 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
514 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
516 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
520 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
522 mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
526 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
529 0, 2),
532 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
536 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
539 0, 2),
542 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
546 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
548 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
553 0, 2),
556 0, 2),
561 0, 2),
565 mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
569 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
571 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
575 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
577 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
581 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
585 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
587 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
591 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
593 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
597 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
603 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
605 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
608 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
610 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
612 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
615 CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
617 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
619 CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
622 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
624 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
628 "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
632 CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
636 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
640 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
642 CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
646 "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
650 "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
654 "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
659 0, 3),
662 0, 3),
667 0, 3),
670 0, 3),
674 "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
676 "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
680 "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
684 "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
686 "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
690 "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
694 "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
696 "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
700 "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
703 0, 3),
706 0, 3),
710 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
712 "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
716 "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
718 "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
722 "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
726 "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
730 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
732 CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
736 "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
740 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
744 "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
746 "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
750 "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
752 "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
756 "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
761 "gout_clkcmu_fsys0_pcie", 1, 4, 0),
768 21, 0, 0),
771 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
773 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
775 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
777 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
780 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
782 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
786 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
790 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
794 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
796 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
801 CLK_IS_CRITICAL, 0),
806 CLK_IS_CRITICAL, 0),
811 21, 0, 0),
816 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
819 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
824 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
827 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
832 21, 0, 0),
835 21, 0, 0),
840 21, 0, 0),
845 21, 0, 0),
848 21, 0, 0),
853 21, 0, 0),
856 21, 0, 0),
861 21, 0, 0),
864 21, 0, 0),
867 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
872 21, 0, 0),
875 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
878 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
882 "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
885 21, 0, 0),
890 21, 0, 0),
893 21, 0, 0),
898 21, 0, 0),
903 21, 0, 0),
907 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
909 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
914 21, CLK_IGNORE_UNUSED, 0),
917 21, CLK_IGNORE_UNUSED, 0),
921 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
926 21, 0, 0),
929 21, 0, 0),
934 21, 0, 0),
937 21, 0, 0),
942 21, CLK_IGNORE_UNUSED, 0),
972 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
973 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600
974 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800
975 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078
976 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080
995 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
1002 0, 0),
1006 0, 0),
1024 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1025 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1026 #define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000
1027 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1028 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000
1029 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004
1030 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008
1051 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1057 CLK_IS_CRITICAL, 0),
1060 CLK_IS_CRITICAL, 0),
1064 CLK_IS_CRITICAL, 0),
1082 /* Register Offset definitions for CMU_DPUM (0x18c00000) */
1083 #define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER 0x0600
1084 #define CLK_CON_DIV_DIV_CLK_DPUM_BUSP 0x1800
1085 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON 0x202c
1086 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA 0x2030
1087 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP 0x2034
1088 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1 0x207c
1089 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1 0x2084
1090 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1 0x208c
1091 #define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1 0x2094
1114 CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3),
1121 0, 0),
1124 0, 0),
1127 0, 0),
1131 0, 0),
1135 0, 0),
1139 0, 0),
1143 0, 0),
1161 /* Register Offset definitions for CMU_FSYS2 (0x17700000) */
1162 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
1163 #define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
1164 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
1166 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
1167 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
1168 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
1169 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
1170 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
1171 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
1173 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
1174 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
1175 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
1176 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
1177 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
1178 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
1179 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
1181 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
1182 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
1183 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
1184 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
1185 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
1186 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
1187 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
1189 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
1190 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
1191 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
1192 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
1193 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
1194 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
1195 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
1197 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
1198 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
1199 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
1200 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
1201 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
1202 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
1259 21, CLK_IGNORE_UNUSED, 0),
1265 21, 0, 0),
1269 21, 0, 0),
1273 21, 0, 0),
1277 21, 0, 0),
1281 21, 0, 0),
1285 21, 0, 0),
1289 21, 0, 0),
1293 21, 0, 0),
1297 21, 0, 0),
1301 21, 0, 0),
1307 21, 0, 0),
1311 21, 0, 0),
1315 21, 0, 0),
1319 21, 0, 0),
1323 21, 0, 0),
1327 21, 0, 0),
1331 21, 0, 0),
1335 21, 0, 0),
1339 21, 0, 0),
1343 21, 0, 0),
1349 21, 0, 0),
1353 21, 0, 0),
1357 21, 0, 0),
1361 21, 0, 0),
1365 21, 0, 0),
1369 21, 0, 0),
1373 21, 0, 0),
1377 21, 0, 0),
1381 21, 0, 0),
1385 21, 0, 0),
1401 /* Register Offset definitions for CMU_FSYS1 (0x17040000) */
1402 #define PLL_LOCKTIME_PLL_MMC 0x0000
1403 #define PLL_CON0_PLL_MMC 0x0100
1404 #define PLL_CON3_PLL_MMC 0x010c
1405 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
1406 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
1407 #define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
1409 #define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
1410 #define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
1412 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
1413 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
1414 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
1416 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
1417 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
1418 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
1419 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
1421 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
1422 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
1423 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
1424 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
1456 0, 1),
1462 CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
1468 21, CLK_IGNORE_UNUSED, 0),
1472 21, CLK_SET_RATE_PARENT, 0),
1476 21, 0, 0),
1480 21, 0, 0),
1484 21, 0, 0),
1488 21, 0, 0),
1492 21, 0, 0),
1496 21, 0, 0),
1500 21, 0, 0),
1504 21, 0, 0),
1508 21, 0, 0),
1528 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1529 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600
1530 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
1531 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
1532 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098
1533 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
1534 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4
1535 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
1567 0, 0),
1571 21, 0, 0),
1575 0, 0),
1579 21, 0, 0),
1595 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1596 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1597 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
1598 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
1599 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
1600 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
1601 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
1602 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
1603 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
1604 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
1605 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
1606 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
1607 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
1608 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
1609 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
1610 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
1611 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
1612 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
1613 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
1614 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
1615 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
1616 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
1617 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
1618 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
1619 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
1620 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
1621 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
1622 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
1623 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
1624 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
1625 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
1626 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
1627 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
1628 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1629 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1630 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1631 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1632 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1633 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1634 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
1635 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
1692 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1694 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1696 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1698 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1700 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1702 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1705 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1712 0, 4),
1715 0, 4),
1718 0, 4),
1721 0, 4),
1724 0, 4),
1727 0, 4),
1730 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1738 21, 0, 0),
1742 21, 0, 0),
1746 21, 0, 0),
1750 21, 0, 0),
1754 21, 0, 0),
1758 21, 0, 0),
1762 21, 0, 0),
1766 21, 0, 0),
1770 21, 0, 0),
1774 21, 0, 0),
1778 21, 0, 0),
1782 21, 0, 0),
1788 21, 0, 0),
1792 21, 0, 0),
1796 21, 0, 0),
1800 21, 0, 0),
1804 21, 0, 0),
1808 21, 0, 0),
1812 21, 0, 0),
1816 21, 0, 0),
1820 21, 0, 0),
1824 21, 0, 0),
1828 21, 0, 0),
1832 21, 0, 0),
1850 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1851 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1852 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
1853 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
1854 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
1855 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
1856 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
1857 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
1858 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
1859 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
1860 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
1861 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
1862 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
1863 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
1864 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
1865 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
1866 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
1867 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
1868 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
1869 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
1870 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
1871 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
1872 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
1873 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
1874 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
1875 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
1876 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
1877 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
1878 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
1879 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
1880 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
1881 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
1882 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
1883 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
1884 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
1885 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
1886 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
1887 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
1888 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
1889 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
1890 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
1947 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1949 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1951 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1953 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1955 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1957 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1960 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1967 0, 4),
1970 0, 4),
1973 0, 4),
1976 0, 4),
1979 0, 4),
1982 0, 4),
1985 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1993 21, 0, 0),
1997 21, 0, 0),
2001 21, 0, 0),
2005 21, 0, 0),
2009 21, 0, 0),
2013 21, 0, 0),
2017 21, 0, 0),
2021 21, 0, 0),
2025 21, 0, 0),
2029 21, 0, 0),
2033 21, 0, 0),
2037 21, 0, 0),
2043 21, 0, 0),
2047 21, 0, 0),
2051 21, 0, 0),
2055 21, 0, 0),
2059 21, 0, 0),
2063 21, 0, 0),
2067 21, 0, 0),
2071 21, 0, 0),
2075 21, 0, 0),
2079 21, 0, 0),
2083 21, 0, 0),
2087 21, 0, 0),
2105 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2106 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
2107 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058
2108 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c
2109 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060
2130 21, CLK_IGNORE_UNUSED, 0),
2133 21, 0, 0),
2136 21, 0, 0),
2158 return 0; in exynosautov9_cmu_probe()