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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml27 pattern: "^memory-controller@[0-9a-f]+$"
62 "^external-memory-controller@[0-9a-f]+$":
95 const: 0
244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */
256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
[all …]
/linux-6.12.1/include/soc/fsl/qe/
Dqe.h34 QE_CLK_NONE = 0,
150 return 0; in cpm_muram_dma()
245 return 0; in qe_alive_during_sleep()
291 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
304 __be32 traps[16]; /* Trap addresses, 0 == ignore */
348 #define BD_STATUS_MASK 0xffff0000
349 #define BD_LENGTH_MASK 0x0000ffff
357 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
358 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
359 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
[all …]
/linux-6.12.1/sound/soc/codecs/
Dcs35l45.h20 #define CS35L45_DEVID 0x00000000
21 #define CS35L45_REVID 0x00000004
22 #define CS35L45_RELID 0x0000000C
23 #define CS35L45_OTPID 0x00000010
24 #define CS35L45_SFT_RESET 0x00000020
25 #define CS35L45_GLOBAL_ENABLES 0x00002014
26 #define CS35L45_BLOCK_ENABLES 0x00002018
27 #define CS35L45_BLOCK_ENABLES2 0x0000201C
28 #define CS35L45_ERROR_RELEASE 0x00002034
29 #define CS35L45_SYNC_GPIO1 0x00002430
[all …]
/linux-6.12.1/arch/arm/net/
Dbpf_jit_32.h12 #define ARM_R0 0
29 #define ARM_COND_EQ 0x0 /* == */
30 #define ARM_COND_NE 0x1 /* != */
31 #define ARM_COND_CS 0x2 /* unsigned >= */
33 #define ARM_COND_CC 0x3 /* unsigned < */
35 #define ARM_COND_MI 0x4 /* < 0 */
36 #define ARM_COND_PL 0x5 /* >= 0 */
37 #define ARM_COND_VS 0x6 /* Signed Overflow */
38 #define ARM_COND_VC 0x7 /* No Signed Overflow */
39 #define ARM_COND_HI 0x8 /* unsigned > */
[all …]
/linux-6.12.1/include/sound/
Dcs35l41.h16 #define CS35L41_FIRSTREG 0x00000000
17 #define CS35L41_LASTREG 0x03804FE8
18 #define CS35L41_DEVID 0x00000000
19 #define CS35L41_REVID 0x00000004
20 #define CS35L41_FABID 0x00000008
21 #define CS35L41_RELID 0x0000000C
22 #define CS35L41_OTPID 0x00000010
23 #define CS35L41_SFT_RESET 0x00000020
24 #define CS35L41_TEST_KEY_CTL 0x00000040
25 #define CS35L41_USER_KEY_CTL 0x00000044
[all …]
/linux-6.12.1/arch/arm64/boot/dts/broadcom/stingray/
Dstingray.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
64 reg = <0x0 0x100>;
72 reg = <0x0 0x101>;
80 reg = <0x0 0x200>;
88 reg = <0x0 0x201>;
96 reg = <0x0 0x300>;
104 reg = <0x0 0x301>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
[all …]
Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux-6.12.1/arch/hexagon/kernel/
Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 CPU_SLEEP_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0 0x80000000 0 0>;
[all …]
Dmsm8976.dtsi26 #clock-cells = <0>;
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0>;
48 reg = <0x1>;
59 reg = <0x2>;
70 reg = <0x3>;
81 reg = <0x100>;
92 reg = <0x101>;
103 reg = <0x102>;
[all …]
Dmsm8953.dtsi25 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0>;
54 reg = <0x1>;
64 reg = <0x2>;
74 reg = <0x3>;
84 reg = <0x100>;
94 reg = <0x101>;
[all …]
Dmsm8939.dtsi30 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #size-cells = <0>;
49 reg = <0x100>;
67 reg = <0x101>;
80 reg = <0x102>;
93 reg = <0x103>;
102 CPU4: cpu@0 {
106 reg = <0x0>;
124 reg = <0x1>;
[all …]
Dmsm8916.dtsi27 reg = <0 0x80000000 0 0>;
36 reg = <0x0 0x86000000 0x0 0x300000>;
42 reg = <0x0 0x86300000 0x0 0x100000>;
50 reg = <0x0 0x86400000 0x0 0x100000>;
55 reg = <0x0 0x86500000 0x0 0x180000>;
60 reg = <0x0 0x86680000 0x0 0x80000>;
66 reg = <0x0 0x86700000 0x0 0xe0000>;
73 reg = <0x0 0x867e0000 0x0 0x20000>;
85 * alignment = <0x0 0x400000>;
86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
[all …]
Dsc8180x.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
[all …]
/linux-6.12.1/drivers/soc/tegra/cbb/
Dtegra194-cbb.c27 #define ERRLOGGER_0_ID_COREID_0 0x00000000
28 #define ERRLOGGER_0_ID_REVISIONID_0 0x00000004
29 #define ERRLOGGER_0_FAULTEN_0 0x00000008
30 #define ERRLOGGER_0_ERRVLD_0 0x0000000c
31 #define ERRLOGGER_0_ERRCLR_0 0x00000010
32 #define ERRLOGGER_0_ERRLOG0_0 0x00000014
33 #define ERRLOGGER_0_ERRLOG1_0 0x00000018
34 #define ERRLOGGER_0_RSVD_00_0 0x0000001c
35 #define ERRLOGGER_0_ERRLOG3_0 0x00000020
36 #define ERRLOGGER_0_ERRLOG4_0 0x00000024
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dtg3.h17 #define TG3_64BIT_REG_HIGH 0x00UL
18 #define TG3_64BIT_REG_LOW 0x04UL
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
23 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
24 #define BDINFO_FLAGS_DISABLED 0x00000002
25 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
28 #define TG3_BDINFO_SIZE 0x10UL
41 #define TG3PCI_VENDOR 0x00000000
[all …]