Lines Matching +full:0 +full:x02c00000
20 #define CS35L45_DEVID 0x00000000
21 #define CS35L45_REVID 0x00000004
22 #define CS35L45_RELID 0x0000000C
23 #define CS35L45_OTPID 0x00000010
24 #define CS35L45_SFT_RESET 0x00000020
25 #define CS35L45_GLOBAL_ENABLES 0x00002014
26 #define CS35L45_BLOCK_ENABLES 0x00002018
27 #define CS35L45_BLOCK_ENABLES2 0x0000201C
28 #define CS35L45_ERROR_RELEASE 0x00002034
29 #define CS35L45_SYNC_GPIO1 0x00002430
30 #define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434
31 #define CS35L45_GPIO3 0x00002438
32 #define CS35L45_PWRMGT_CTL 0x00002900
33 #define CS35L45_WAKESRC_CTL 0x00002904
34 #define CS35L45_WKI2C_CTL 0x00002908
35 #define CS35L45_PWRMGT_STS 0x0000290C
36 #define CS35L45_REFCLK_INPUT 0x00002C04
37 #define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C
38 #define CS35L45_BOOST_CCM_CFG 0x00003808
39 #define CS35L45_BOOST_DCM_CFG 0x0000380C
40 #define CS35L45_BOOST_OV_CFG 0x0000382C
41 #define CS35L45_ASP_ENABLES1 0x00004800
42 #define CS35L45_ASP_CONTROL1 0x00004804
43 #define CS35L45_ASP_CONTROL2 0x00004808
44 #define CS35L45_ASP_CONTROL3 0x0000480C
45 #define CS35L45_ASP_FRAME_CONTROL1 0x00004810
46 #define CS35L45_ASP_FRAME_CONTROL2 0x00004814
47 #define CS35L45_ASP_FRAME_CONTROL5 0x00004820
48 #define CS35L45_ASP_DATA_CONTROL1 0x00004830
49 #define CS35L45_ASP_DATA_CONTROL5 0x00004840
50 #define CS35L45_DACPCM1_INPUT 0x00004C00
51 #define CS35L45_ASPTX1_INPUT 0x00004C20
52 #define CS35L45_ASPTX2_INPUT 0x00004C24
53 #define CS35L45_ASPTX3_INPUT 0x00004C28
54 #define CS35L45_ASPTX4_INPUT 0x00004C2C
55 #define CS35L45_ASPTX5_INPUT 0x00004C30
56 #define CS35L45_DSP1RX1_INPUT 0x00004C40
57 #define CS35L45_DSP1RX2_INPUT 0x00004C44
58 #define CS35L45_DSP1RX3_INPUT 0x00004C48
59 #define CS35L45_DSP1RX4_INPUT 0x00004C4C
60 #define CS35L45_DSP1RX5_INPUT 0x00004C50
61 #define CS35L45_DSP1RX6_INPUT 0x00004C54
62 #define CS35L45_DSP1RX7_INPUT 0x00004C58
63 #define CS35L45_DSP1RX8_INPUT 0x00004C5C
64 #define CS35L45_HVLV_CONFIG 0x00006400
65 #define CS35L45_LDPM_CONFIG 0x00006404
66 #define CS35L45_AMP_PCM_CONTROL 0x00007000
67 #define CS35L45_AMP_PCM_HPF_TST 0x00007004
68 #define CS35L45_AMP_GAIN 0x00007800
69 #define CS35L45_IRQ1_CFG 0x0000E000
70 #define CS35L45_IRQ1_STATUS 0x0000E004
71 #define CS35L45_IRQ1_EINT_1 0x0000E010
72 #define CS35L45_IRQ1_EINT_2 0x0000E014
73 #define CS35L45_IRQ1_EINT_3 0x0000E018
74 #define CS35L45_IRQ1_EINT_4 0x0000E01C
75 #define CS35L45_IRQ1_EINT_5 0x0000E020
76 #define CS35L45_IRQ1_EINT_7 0x0000E028
77 #define CS35L45_IRQ1_EINT_8 0x0000E02C
78 #define CS35L45_IRQ1_EINT_18 0x0000E054
79 #define CS35L45_IRQ1_STS_1 0x0000E090
80 #define CS35L45_IRQ1_STS_2 0x0000E094
81 #define CS35L45_IRQ1_STS_3 0x0000E098
82 #define CS35L45_IRQ1_STS_4 0x0000E09C
83 #define CS35L45_IRQ1_STS_5 0x0000E0A0
84 #define CS35L45_IRQ1_STS_7 0x0000E0A8
85 #define CS35L45_IRQ1_STS_8 0x0000E0AC
86 #define CS35L45_IRQ1_STS_18 0x0000E0D4
87 #define CS35L45_IRQ1_MASK_1 0x0000E110
88 #define CS35L45_IRQ1_MASK_2 0x0000E114
89 #define CS35L45_IRQ1_MASK_3 0x0000E118
90 #define CS35L45_IRQ1_MASK_4 0x0000E11C
91 #define CS35L45_IRQ1_MASK_5 0x0000E120
92 #define CS35L45_IRQ1_MASK_6 0x0000E124
93 #define CS35L45_IRQ1_MASK_7 0x0000E128
94 #define CS35L45_IRQ1_MASK_8 0x0000E12C
95 #define CS35L45_IRQ1_MASK_9 0x0000E130
96 #define CS35L45_IRQ1_MASK_10 0x0000E134
97 #define CS35L45_IRQ1_MASK_11 0x0000E138
98 #define CS35L45_IRQ1_MASK_12 0x0000E13C
99 #define CS35L45_IRQ1_MASK_13 0x0000E140
100 #define CS35L45_IRQ1_MASK_14 0x0000E144
101 #define CS35L45_IRQ1_MASK_15 0x0000E148
102 #define CS35L45_IRQ1_MASK_16 0x0000E14C
103 #define CS35L45_IRQ1_MASK_17 0x0000E150
104 #define CS35L45_IRQ1_MASK_18 0x0000E154
105 #define CS35L45_GPIO_STATUS1 0x0000F000
106 #define CS35L45_GPIO1_CTRL1 0x0000F008
107 #define CS35L45_GPIO2_CTRL1 0x0000F00C
108 #define CS35L45_GPIO3_CTRL1 0x0000F010
109 #define CS35L45_DSP_MBOX_1 0x00011000
110 #define CS35L45_DSP_MBOX_2 0x00011004
111 #define CS35L45_DSP_VIRT1_MBOX_1 0x00011020
112 #define CS35L45_DSP_VIRT1_MBOX_2 0x00011024
113 #define CS35L45_DSP_VIRT1_MBOX_3 0x00011028
114 #define CS35L45_DSP_VIRT1_MBOX_4 0x0001102C
115 #define CS35L45_DSP_VIRT2_MBOX_1 0x00011040
116 #define CS35L45_DSP_VIRT2_MBOX_2 0x00011044
117 #define CS35L45_DSP_VIRT2_MBOX_3 0x00011048
118 #define CS35L45_DSP_VIRT2_MBOX_4 0x0001104C
119 #define CS35L45_DSP1_XMEM_PACK_0 0x02000000
120 #define CS35L45_DSP1_XMEM_PACK_4607 0x020047FC
121 #define CS35L45_DSP1_XMEM_UNPACK32_0 0x02400000
122 #define CS35L45_DSP1_XMEM_UNPACK32_3071 0x02402FFC
123 #define CS35L45_DSP1_SYS_ID 0x025E0000
124 #define CS35L45_DSP1_XMEM_UNPACK24_0 0x02800000
125 #define CS35L45_DSP1_XMEM_UNPACK24_6143 0x02805FFC
126 #define CS35L45_DSP1_CLOCK_FREQ 0x02B80000
127 #define CS35L45_DSP1_RX1_RATE 0x02B80080
128 #define CS35L45_DSP1_RX2_RATE 0x02B80088
129 #define CS35L45_DSP1_RX3_RATE 0x02B80090
130 #define CS35L45_DSP1_RX4_RATE 0x02B80098
131 #define CS35L45_DSP1_RX5_RATE 0x02B800A0
132 #define CS35L45_DSP1_RX6_RATE 0x02B800A8
133 #define CS35L45_DSP1_RX7_RATE 0x02B800B0
134 #define CS35L45_DSP1_RX8_RATE 0x02B800B8
135 #define CS35L45_DSP1_TX1_RATE 0x02B80280
136 #define CS35L45_DSP1_TX2_RATE 0x02B80288
137 #define CS35L45_DSP1_TX3_RATE 0x02B80290
138 #define CS35L45_DSP1_TX4_RATE 0x02B80298
139 #define CS35L45_DSP1_TX5_RATE 0x02B802A0
140 #define CS35L45_DSP1_TX6_RATE 0x02B802A8
141 #define CS35L45_DSP1_TX7_RATE 0x02B802B0
142 #define CS35L45_DSP1_TX8_RATE 0x02B802B8
143 #define CS35L45_DSP1_SCRATCH1 0x02B805C0
144 #define CS35L45_DSP1_SCRATCH2 0x02B805C8
145 #define CS35L45_DSP1_SCRATCH3 0x02B805D0
146 #define CS35L45_DSP1_SCRATCH4 0x02B805D8
147 #define CS35L45_DSP1_CCM_CORE_CONTROL 0x02BC1000
148 #define CS35L45_DSP1_YMEM_PACK_0 0x02C00000
149 #define CS35L45_DSP1_YMEM_PACK_1532 0x02C017F0
150 #define CS35L45_DSP1_YMEM_UNPACK32_0 0x03000000
151 #define CS35L45_DSP1_YMEM_UNPACK32_1022 0x03000FF8
152 #define CS35L45_DSP1_YMEM_UNPACK24_0 0x03400000
153 #define CS35L45_DSP1_YMEM_UNPACK24_2043 0x03401FEC
154 #define CS35L45_DSP1_PMEM_0 0x03800000
155 #define CS35L45_DSP1_PMEM_3834 0x03803BE8
156 #define CS35L45_LASTREG 0x03C6EFE8
159 #define CS35L45_SOFT_RESET_TRIGGER 0x5A000000
162 #define CS35L45_GLOBAL_EN_SHIFT 0
163 #define CS35L45_GLOBAL_EN_MASK BIT(0)
175 #define CS35L45_AMP_EN_SHIFT 0
176 #define CS35L45_AMP_EN_MASK BIT(0)
178 #define CS35L45_BST_DISABLE_FET_OFF 0x00
179 #define CS35L45_BST_DISABLE_FET_ON 0x01
180 #define CS35L45_BST_ENABLE 0x02
197 #define CS35L45_CCM_CORE_EN_SHIFT 0
198 #define CS35L45_CCM_CORE_EN_MASK BIT(0)
209 #define CS35L45_PLL_REFCLK_SEL_SHIFT 0
210 #define CS35L45_PLL_REFCLK_SEL_MASK GENMASK(2, 0)
212 #define CS35L45_PLL_REFCLK_SEL_BCLK 0x0
215 #define CS35L45_GLOBAL_FS_SHIFT 0
216 #define CS35L45_GLOBAL_FS_MASK GENMASK(4, 0)
218 #define CS35L45_48P0_KHZ 0x03
219 #define CS35L45_96P0_KHZ 0x04
220 #define CS35L45_44P100_KHZ 0x0B
221 #define CS35L45_88P200_KHZ 0x0C
230 #define CS35L45_ASP_TX1_EN_SHIFT 0
244 #define CS35l45_ASP_FMT_DSP_A 0
248 #define CS35L45_ASP_DOUT_HIZ_CTRL_SHIFT 0
249 #define CS35L45_ASP_DOUT_HIZ_CTRL_MASK GENMASK(1, 0)
258 #define CS35L45_ASP_TX1_SLOT_SHIFT 0
259 #define CS35L45_ASP_TX1_SLOT_MASK GENMASK(5, 0)
268 #define CS35L45_ASP_RX1_SLOT_SHIFT 0
269 #define CS35L45_ASP_RX1_SLOT_MASK GENMASK(5, 0)
276 #define CS35L45_ASP_WL_SHIFT 0
277 #define CS35L45_ASP_WL_MASK GENMASK(5, 0)
280 #define CS35L45_FORCE_LV_OPERATION 0x01
281 #define CS35L45_FORCE_HV_OPERATION 0x02
282 #define CS35L45_HVLV_OPERATION 0x03
283 #define CS35L45_HVLV_MODE_SHIFT 0
284 #define CS35L45_HVLV_MODE_MASK GENMASK(1, 0)
287 #define CS35L45_AMP_VOL_PCM_SHIFT 0
291 #define CS35l45_HPF_DEFAULT 0x00000000
292 #define CS35L45_HPF_44P1 0x000108BD
293 #define CS35L45_HPF_88P2 0x0001045F
296 #define CS35L45_AMP_GAIN_PCM_10DBV 0x00
297 #define CS35L45_AMP_GAIN_PCM_13DBV 0x01
298 #define CS35L45_AMP_GAIN_PCM_16DBV 0x02
299 #define CS35L45_AMP_GAIN_PCM_19DBV 0x03
306 #define CS35L45_OTP_BUSY_MASK BIT(0)
359 #define CS35L45_PCM_SRC_MASK 0x7F
360 #define CS35L45_PCM_SRC_ZERO 0x00
361 #define CS35L45_PCM_SRC_ASP_RX1 0x08
362 #define CS35L45_PCM_SRC_ASP_RX2 0x09
363 #define CS35L45_PCM_SRC_VMON 0x18
364 #define CS35L45_PCM_SRC_IMON 0x19
365 #define CS35L45_PCM_SRC_ERR_VOL 0x20
366 #define CS35L45_PCM_SRC_CLASSH_TGT 0x21
367 #define CS35L45_PCM_SRC_VDD_BATTMON 0x28
368 #define CS35L45_PCM_SRC_VDD_BSTMON 0x29
369 #define CS35L45_PCM_SRC_DSP_TX1 0x32
370 #define CS35L45_PCM_SRC_DSP_TX2 0x33
371 #define CS35L45_PCM_SRC_TEMPMON 0x3A
372 #define CS35L45_PCM_SRC_INTERPOLATOR 0x40
373 #define CS35L45_PCM_SRC_IL_TARGET 0x48
381 #define CS35L45_WKSRC_SYNC_GPIO1 BIT(0)
390 #define CS35L45_WKSRC_POL_SHIFT 0
391 #define CS35L45_WKSRC_POL_MASK GENMASK(3, 0)
396 #define CS35L45_WKI2C_ADDR_SHIFT 0
397 #define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0)
402 CSPL_MBOX_STS_RUNNING = 0,
409 CSPL_MBOX_CMD_NONE = 0,
421 CONTROL_BUS_I2C = 0,
426 AMP_MODE_SPK = 0,
477 #define CS35L45_MBOX3_CMD_MASK 0xFF
478 #define CS35L45_MBOX3_CMD_SHIFT 0
479 #define CS35L45_MBOX3_DATA_MASK 0xFFFFFF00
483 EVENT_SPEAKER_STATUS = 0x66,
484 EVENT_BOOT_DONE = 0x67,