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/linux-6.12.1/drivers/usb/storage/
Dunusual_devs.h56 UNUSUAL_DEV( 0x03eb, 0x2002, 0x0100, 0x0100,
63 UNUSUAL_DEV( 0x03ee, 0x6906, 0x0003, 0x0003,
69 UNUSUAL_DEV( 0x03f0, 0x0107, 0x0200, 0x0200,
72 USB_SC_8070, USB_PR_CB, NULL, 0),
75 UNUSUAL_DEV( 0x03f0, 0x070c, 0x0000, 0x0000,
85 UNUSUAL_DEV( 0x03f0, 0x4002, 0x0001, 0x0001,
90 UNUSUAL_DEV( 0x03f3, 0x0001, 0x0000, 0x9999,
101 UNUSUAL_DEV( 0x0409, 0x0040, 0x0000, 0x9999,
108 UNUSUAL_DEV( 0x040d, 0x6205, 0x0003, 0x0003,
119 UNUSUAL_DEV( 0x0411, 0x001c, 0x0113, 0x0113,
[all …]
Dunusual_sddr09.h9 UNUSUAL_DEV( 0x0436, 0x0005, 0x0100, 0x0100,
12 USB_SC_SCSI, USB_PR_DPCM_USB, NULL, 0),
14 UNUSUAL_DEV( 0x04e6, 0x0003, 0x0000, 0x9999,
18 0),
21 UNUSUAL_DEV( 0x04e6, 0x0005, 0x0100, 0x0208,
25 0),
27 UNUSUAL_DEV( 0x066b, 0x0105, 0x0100, 0x0100,
31 0),
33 UNUSUAL_DEV( 0x0781, 0x0200, 0x0000, 0x9999,
37 0),
[all …]
Dunusual_isd200.h9 UNUSUAL_DEV( 0x054c, 0x002b, 0x0100, 0x0110,
13 0),
15 UNUSUAL_DEV( 0x05ab, 0x0031, 0x0100, 0x0110,
19 0),
21 UNUSUAL_DEV( 0x05ab, 0x0301, 0x0100, 0x0110,
25 0),
27 UNUSUAL_DEV( 0x05ab, 0x0351, 0x0100, 0x0110,
31 0),
33 UNUSUAL_DEV( 0x05ab, 0x5701, 0x0100, 0x0110,
37 0),
[all …]
/linux-6.12.1/sound/soc/codecs/
Dwm8985.h13 #define WM8985_SOFTWARE_RESET 0x00
14 #define WM8985_POWER_MANAGEMENT_1 0x01
15 #define WM8985_POWER_MANAGEMENT_2 0x02
16 #define WM8985_POWER_MANAGEMENT_3 0x03
17 #define WM8985_AUDIO_INTERFACE 0x04
18 #define WM8985_COMPANDING_CONTROL 0x05
19 #define WM8985_CLOCK_GEN_CONTROL 0x06
20 #define WM8985_ADDITIONAL_CONTROL 0x07
21 #define WM8985_GPIO_CONTROL 0x08
22 #define WM8985_JACK_DETECT_CONTROL_1 0x09
[all …]
Dwm8983.h16 #define WM8983_SOFTWARE_RESET 0x00
17 #define WM8983_POWER_MANAGEMENT_1 0x01
18 #define WM8983_POWER_MANAGEMENT_2 0x02
19 #define WM8983_POWER_MANAGEMENT_3 0x03
20 #define WM8983_AUDIO_INTERFACE 0x04
21 #define WM8983_COMPANDING_CONTROL 0x05
22 #define WM8983_CLOCK_GEN_CONTROL 0x06
23 #define WM8983_ADDITIONAL_CONTROL 0x07
24 #define WM8983_GPIO_CONTROL 0x08
25 #define WM8983_JACK_DETECT_CONTROL_1 0x09
[all …]
Dwm8955.h18 #define WM8955_LOUT1_VOLUME 0x02
19 #define WM8955_ROUT1_VOLUME 0x03
20 #define WM8955_DAC_CONTROL 0x05
21 #define WM8955_AUDIO_INTERFACE 0x07
22 #define WM8955_SAMPLE_RATE 0x08
23 #define WM8955_LEFT_DAC_VOLUME 0x0A
24 #define WM8955_RIGHT_DAC_VOLUME 0x0B
25 #define WM8955_BASS_CONTROL 0x0C
26 #define WM8955_TREBLE_CONTROL 0x0D
27 #define WM8955_RESET 0x0F
[all …]
Dwm9090.h16 #define WM9090_SOFTWARE_RESET 0x00
17 #define WM9090_POWER_MANAGEMENT_1 0x01
18 #define WM9090_POWER_MANAGEMENT_2 0x02
19 #define WM9090_POWER_MANAGEMENT_3 0x03
20 #define WM9090_CLOCKING_1 0x06
21 #define WM9090_IN1_LINE_CONTROL 0x16
22 #define WM9090_IN2_LINE_CONTROL 0x17
23 #define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18
24 #define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19
25 #define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A
[all …]
Dwm8961.h14 #define WM8961_BCLK_DIV_1 0
32 #define WM8961_LEFT_INPUT_VOLUME 0x00
33 #define WM8961_RIGHT_INPUT_VOLUME 0x01
34 #define WM8961_LOUT1_VOLUME 0x02
35 #define WM8961_ROUT1_VOLUME 0x03
36 #define WM8961_CLOCKING1 0x04
37 #define WM8961_ADC_DAC_CONTROL_1 0x05
38 #define WM8961_ADC_DAC_CONTROL_2 0x06
39 #define WM8961_AUDIO_INTERFACE_0 0x07
40 #define WM8961_CLOCKING2 0x08
[all …]
Dwm8993.h15 #define WM8993_SOFTWARE_RESET 0x00
16 #define WM8993_POWER_MANAGEMENT_1 0x01
17 #define WM8993_POWER_MANAGEMENT_2 0x02
18 #define WM8993_POWER_MANAGEMENT_3 0x03
19 #define WM8993_AUDIO_INTERFACE_1 0x04
20 #define WM8993_AUDIO_INTERFACE_2 0x05
21 #define WM8993_CLOCKING_1 0x06
22 #define WM8993_CLOCKING_2 0x07
23 #define WM8993_AUDIO_INTERFACE_3 0x08
24 #define WM8993_AUDIO_INTERFACE_4 0x09
[all …]
Dwm8990.h16 #define WM8990_RESET 0x00
17 #define WM8990_POWER_MANAGEMENT_1 0x01
18 #define WM8990_POWER_MANAGEMENT_2 0x02
19 #define WM8990_POWER_MANAGEMENT_3 0x03
20 #define WM8990_AUDIO_INTERFACE_1 0x04
21 #define WM8990_AUDIO_INTERFACE_2 0x05
22 #define WM8990_CLOCKING_1 0x06
23 #define WM8990_CLOCKING_2 0x07
24 #define WM8990_AUDIO_INTERFACE_3 0x08
25 #define WM8990_AUDIO_INTERFACE_4 0x09
[all …]
Dwm8991.h16 #define WM8991_RESET 0x00
17 #define WM8991_POWER_MANAGEMENT_1 0x01
18 #define WM8991_POWER_MANAGEMENT_2 0x02
19 #define WM8991_POWER_MANAGEMENT_3 0x03
20 #define WM8991_AUDIO_INTERFACE_1 0x04
21 #define WM8991_AUDIO_INTERFACE_2 0x05
22 #define WM8991_CLOCKING_1 0x06
23 #define WM8991_CLOCKING_2 0x07
24 #define WM8991_AUDIO_INTERFACE_3 0x08
25 #define WM8991_AUDIO_INTERFACE_4 0x09
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/
Dradeon_ucode.h75 #define RV770_SMC_UCODE_START 0x0100
76 #define RV770_SMC_UCODE_SIZE 0x410d
77 #define RV770_SMC_INT_VECTOR_START 0xffc0
78 #define RV770_SMC_INT_VECTOR_SIZE 0x0040
80 #define RV730_SMC_UCODE_START 0x0100
81 #define RV730_SMC_UCODE_SIZE 0x412c
82 #define RV730_SMC_INT_VECTOR_START 0xffc0
83 #define RV730_SMC_INT_VECTOR_SIZE 0x0040
85 #define RV710_SMC_UCODE_START 0x0100
86 #define RV710_SMC_UCODE_SIZE 0x3f1f
[all …]
/linux-6.12.1/include/linux/mfd/madera/
Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux-6.12.1/include/linux/mfd/wm8350/
Dcore.h27 #define WM8350_RESET_ID 0x00
28 #define WM8350_ID 0x01
29 #define WM8350_REVISION 0x02
30 #define WM8350_SYSTEM_CONTROL_1 0x03
31 #define WM8350_SYSTEM_CONTROL_2 0x04
32 #define WM8350_SYSTEM_HIBERNATE 0x05
33 #define WM8350_INTERFACE_CONTROL 0x06
34 #define WM8350_POWER_MGMT_1 0x08
35 #define WM8350_POWER_MGMT_2 0x09
36 #define WM8350_POWER_MGMT_3 0x0A
[all …]
Daudio.h13 #define WM8350_CLOCK_CONTROL_1 0x28
14 #define WM8350_CLOCK_CONTROL_2 0x29
15 #define WM8350_FLL_CONTROL_1 0x2A
16 #define WM8350_FLL_CONTROL_2 0x2B
17 #define WM8350_FLL_CONTROL_3 0x2C
18 #define WM8350_FLL_CONTROL_4 0x2D
19 #define WM8350_DAC_CONTROL 0x30
20 #define WM8350_DAC_DIGITAL_VOLUME_L 0x32
21 #define WM8350_DAC_DIGITAL_VOLUME_R 0x33
22 #define WM8350_DAC_LR_RATE 0x35
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra30-cpu-opp.dtsi10 opp-supported-hw = <0x1F 0x31FE>;
16 opp-supported-hw = <0x1F 0x0C01>;
22 opp-supported-hw = <0x1F 0x0200>;
28 opp-supported-hw = <0x1F 0x31FE>;
34 opp-supported-hw = <0x1F 0x0C01>;
40 opp-supported-hw = <0x1F 0x0200>;
46 opp-supported-hw = <0x1F 0x31FE>;
53 opp-supported-hw = <0x1F 0x0C01>;
60 opp-supported-hw = <0x1F 0x0200>;
67 opp-supported-hw = <0x1F 0x0C00>;
[all …]
/linux-6.12.1/include/linux/mfd/wm831x/
Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
Dirq.h14 #define WM831X_IRQ_TEMP_THW 0
75 * R16400 (0x4010) - System Interrupts
77 #define WM831X_PS_INT 0x8000 /* PS_INT */
78 #define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
81 #define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
82 #define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
85 #define WM831X_GP_INT 0x2000 /* GP_INT */
86 #define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
89 #define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
90 #define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
[all …]
/linux-6.12.1/drivers/net/ethernet/cirrus/
Dcs89x0.h18 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
22 #define PP_ISAIOB 0x0020 /* IO base address */
23 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
24 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
25 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
26 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
27 #define PP_ISASOF 0x0026 /* ISA DMA offset */
28 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
29 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
30 #define PP_CS8900_ISAMemB 0x002C /* Memory base */
[all …]
/linux-6.12.1/sound/soc/fsl/
Dimx-pcm-rpmsg.h9 * A SRTM message consists of a 10 bytes header followed by 0~N bytes of data
14 * | Byte Offset | 7 6 5 4 3 2 1 0 |
16 * | 0 | Category |
34 * | 10 | DATA 0 |
44 * | Category | 0 | The destination category. |
66 * | 0x03 | 0x0100 | 0x00 | 0x00 | Data[0]: Audio Device Index | Open a TX Instance. |
75 * | 0x03 | 0x0100 | 0x00 | 0x01 | Data[0]: Audio Device Index | Start a TX Instance. |
78 * | 0x03 | 0x0100 | 0x00 | 0x02 | Data[0]: Audio Device Index | Pause a TX Instance. |
81 * | 0x03 | 0x0100 | 0x00 | 0x03 | Data[0]: Audio Device Index | Resume a TX Instance. |
83 * | 0x03 | 0x0100 | 0x00 | 0x04 | Data[0]: Audio Device Index | Stop a TX Instance. |
[all …]
/linux-6.12.1/include/linux/usb/
Dr8a66597.h13 #define R8A66597_PLATDATA_XTAL_12MHZ 0x01
14 #define R8A66597_PLATDATA_XTAL_24MHZ 0x02
15 #define R8A66597_PLATDATA_XTAL_48MHZ 0x03
44 #define SYSCFG0 0x00
45 #define SYSCFG1 0x02
46 #define SYSSTS0 0x04
47 #define SYSSTS1 0x06
48 #define DVSTCTR0 0x08
49 #define DVSTCTR1 0x0A
50 #define TESTMODE 0x0C
[all …]
/linux-6.12.1/include/linux/mfd/
Dwm8400-audio.h14 * R2 (0x02) - Power Management (1)
16 #define WM8400_CODEC_ENA 0x8000 /* CODEC_ENA */
17 #define WM8400_CODEC_ENA_MASK 0x8000 /* CODEC_ENA */
20 #define WM8400_SYSCLK_ENA 0x4000 /* SYSCLK_ENA */
21 #define WM8400_SYSCLK_ENA_MASK 0x4000 /* SYSCLK_ENA */
24 #define WM8400_SPK_MIX_ENA 0x2000 /* SPK_MIX_ENA */
25 #define WM8400_SPK_MIX_ENA_MASK 0x2000 /* SPK_MIX_ENA */
28 #define WM8400_SPK_ENA 0x1000 /* SPK_ENA */
29 #define WM8400_SPK_ENA_MASK 0x1000 /* SPK_ENA */
32 #define WM8400_OUT3_ENA 0x0800 /* OUT3_ENA */
[all …]
/linux-6.12.1/drivers/media/i2c/
Dsony-btf-mpx.c21 MODULE_PARM_DESC(debug, "debug level 0=off(default) 1=on");
29 * IF/MPX address: 0x42/0x40 0x43/0x44
52 buffer[0] = dev; in mpx_write()
54 buffer[2] = addr & 0xff; in mpx_write()
56 buffer[4] = val & 0xff; in mpx_write()
58 msg.flags = 0; in mpx_write()
62 return 0; in mpx_write()
97 * For Asia, replace the 0x26XX in FM_PRESCALE with 0x14XX.
102 * 0x01 MAIN SUB
103 * 0x03 MAIN MAIN
[all …]
/linux-6.12.1/arch/sh/include/asm/
Dsmc37c93x.h14 #define FDC_PRIMARY_BASE 0x3f0
15 #define IDE1_PRIMARY_BASE 0x1f0
16 #define IDE1_SECONDARY_BASE 0x170
17 #define PARPORT_PRIMARY_BASE 0x378
18 #define COM1_PRIMARY_BASE 0x2f8
19 #define COM2_PRIMARY_BASE 0x3f8
20 #define RTC_PRIMARY_BASE 0x070
21 #define KBC_PRIMARY_BASE 0x060
22 #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
25 #define LDN_FDC 0
[all …]
/linux-6.12.1/sound/pci/oxygen/
Dcm9780.h5 #define CM9780_JACK 0x62
6 #define CM9780_MIXER 0x64
7 #define CM9780_GPIO_SETUP 0x70
8 #define CM9780_GPIO_STATUS 0x72
11 #define CM9780_RSOE 0x0001
12 #define CM9780_CBOE 0x0002
13 #define CM9780_SSOE 0x0004
14 #define CM9780_FROE 0x0008
15 #define CM9780_HP2FMICOE 0x0010
16 #define CM9780_CB2MICOE 0x0020
[all …]

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