Lines Matching +full:0 +full:x0100
16 #define WM9090_SOFTWARE_RESET 0x00
17 #define WM9090_POWER_MANAGEMENT_1 0x01
18 #define WM9090_POWER_MANAGEMENT_2 0x02
19 #define WM9090_POWER_MANAGEMENT_3 0x03
20 #define WM9090_CLOCKING_1 0x06
21 #define WM9090_IN1_LINE_CONTROL 0x16
22 #define WM9090_IN2_LINE_CONTROL 0x17
23 #define WM9090_IN1_LINE_INPUT_A_VOLUME 0x18
24 #define WM9090_IN1_LINE_INPUT_B_VOLUME 0x19
25 #define WM9090_IN2_LINE_INPUT_A_VOLUME 0x1A
26 #define WM9090_IN2_LINE_INPUT_B_VOLUME 0x1B
27 #define WM9090_LEFT_OUTPUT_VOLUME 0x1C
28 #define WM9090_RIGHT_OUTPUT_VOLUME 0x1D
29 #define WM9090_SPKMIXL_ATTENUATION 0x22
30 #define WM9090_SPKOUT_MIXERS 0x24
31 #define WM9090_CLASSD3 0x25
32 #define WM9090_SPEAKER_VOLUME_LEFT 0x26
33 #define WM9090_OUTPUT_MIXER1 0x2D
34 #define WM9090_OUTPUT_MIXER2 0x2E
35 #define WM9090_OUTPUT_MIXER3 0x2F
36 #define WM9090_OUTPUT_MIXER4 0x30
37 #define WM9090_SPEAKER_MIXER 0x36
38 #define WM9090_ANTIPOP2 0x39
39 #define WM9090_WRITE_SEQUENCER_0 0x46
40 #define WM9090_WRITE_SEQUENCER_1 0x47
41 #define WM9090_WRITE_SEQUENCER_2 0x48
42 #define WM9090_WRITE_SEQUENCER_3 0x49
43 #define WM9090_WRITE_SEQUENCER_4 0x4A
44 #define WM9090_WRITE_SEQUENCER_5 0x4B
45 #define WM9090_CHARGE_PUMP_1 0x4C
46 #define WM9090_DC_SERVO_0 0x54
47 #define WM9090_DC_SERVO_1 0x55
48 #define WM9090_DC_SERVO_3 0x57
49 #define WM9090_DC_SERVO_READBACK_0 0x58
50 #define WM9090_DC_SERVO_READBACK_1 0x59
51 #define WM9090_DC_SERVO_READBACK_2 0x5A
52 #define WM9090_ANALOGUE_HP_0 0x60
53 #define WM9090_AGC_CONTROL_0 0x62
54 #define WM9090_AGC_CONTROL_1 0x63
55 #define WM9090_AGC_CONTROL_2 0x64
58 #define WM9090_MAX_REGISTER 0x64
65 * R0 (0x00) - Software Reset
67 #define WM9090_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */
68 #define WM9090_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */
69 #define WM9090_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */
72 * R1 (0x01) - Power Management (1)
74 #define WM9090_SPKOUTL_ENA 0x1000 /* SPKOUTL_ENA */
75 #define WM9090_SPKOUTL_ENA_MASK 0x1000 /* SPKOUTL_ENA */
78 #define WM9090_HPOUT1L_ENA 0x0200 /* HPOUT1L_ENA */
79 #define WM9090_HPOUT1L_ENA_MASK 0x0200 /* HPOUT1L_ENA */
82 #define WM9090_HPOUT1R_ENA 0x0100 /* HPOUT1R_ENA */
83 #define WM9090_HPOUT1R_ENA_MASK 0x0100 /* HPOUT1R_ENA */
86 #define WM9090_OSC_ENA 0x0008 /* OSC_ENA */
87 #define WM9090_OSC_ENA_MASK 0x0008 /* OSC_ENA */
90 #define WM9090_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */
93 #define WM9090_BIAS_ENA 0x0001 /* BIAS_ENA */
94 #define WM9090_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */
95 #define WM9090_BIAS_ENA_SHIFT 0 /* BIAS_ENA */
99 * R2 (0x02) - Power Management (2)
101 #define WM9090_TSHUT 0x8000 /* TSHUT */
102 #define WM9090_TSHUT_MASK 0x8000 /* TSHUT */
105 #define WM9090_TSHUT_ENA 0x4000 /* TSHUT_ENA */
106 #define WM9090_TSHUT_ENA_MASK 0x4000 /* TSHUT_ENA */
109 #define WM9090_TSHUT_OPDIS 0x2000 /* TSHUT_OPDIS */
110 #define WM9090_TSHUT_OPDIS_MASK 0x2000 /* TSHUT_OPDIS */
113 #define WM9090_IN1A_ENA 0x0080 /* IN1A_ENA */
114 #define WM9090_IN1A_ENA_MASK 0x0080 /* IN1A_ENA */
117 #define WM9090_IN1B_ENA 0x0040 /* IN1B_ENA */
118 #define WM9090_IN1B_ENA_MASK 0x0040 /* IN1B_ENA */
121 #define WM9090_IN2A_ENA 0x0020 /* IN2A_ENA */
122 #define WM9090_IN2A_ENA_MASK 0x0020 /* IN2A_ENA */
125 #define WM9090_IN2B_ENA 0x0010 /* IN2B_ENA */
126 #define WM9090_IN2B_ENA_MASK 0x0010 /* IN2B_ENA */
131 * R3 (0x03) - Power Management (3)
133 #define WM9090_AGC_ENA 0x4000 /* AGC_ENA */
134 #define WM9090_AGC_ENA_MASK 0x4000 /* AGC_ENA */
137 #define WM9090_SPKLVOL_ENA 0x0100 /* SPKLVOL_ENA */
138 #define WM9090_SPKLVOL_ENA_MASK 0x0100 /* SPKLVOL_ENA */
141 #define WM9090_MIXOUTL_ENA 0x0020 /* MIXOUTL_ENA */
142 #define WM9090_MIXOUTL_ENA_MASK 0x0020 /* MIXOUTL_ENA */
145 #define WM9090_MIXOUTR_ENA 0x0010 /* MIXOUTR_ENA */
146 #define WM9090_MIXOUTR_ENA_MASK 0x0010 /* MIXOUTR_ENA */
149 #define WM9090_SPKMIX_ENA 0x0008 /* SPKMIX_ENA */
150 #define WM9090_SPKMIX_ENA_MASK 0x0008 /* SPKMIX_ENA */
155 * R6 (0x06) - Clocking 1
157 #define WM9090_TOCLK_RATE 0x8000 /* TOCLK_RATE */
158 #define WM9090_TOCLK_RATE_MASK 0x8000 /* TOCLK_RATE */
161 #define WM9090_TOCLK_ENA 0x4000 /* TOCLK_ENA */
162 #define WM9090_TOCLK_ENA_MASK 0x4000 /* TOCLK_ENA */
167 * R22 (0x16) - IN1 Line Control
169 #define WM9090_IN1_DIFF 0x0002 /* IN1_DIFF */
170 #define WM9090_IN1_DIFF_MASK 0x0002 /* IN1_DIFF */
173 #define WM9090_IN1_CLAMP 0x0001 /* IN1_CLAMP */
174 #define WM9090_IN1_CLAMP_MASK 0x0001 /* IN1_CLAMP */
175 #define WM9090_IN1_CLAMP_SHIFT 0 /* IN1_CLAMP */
179 * R23 (0x17) - IN2 Line Control
181 #define WM9090_IN2_DIFF 0x0002 /* IN2_DIFF */
182 #define WM9090_IN2_DIFF_MASK 0x0002 /* IN2_DIFF */
185 #define WM9090_IN2_CLAMP 0x0001 /* IN2_CLAMP */
186 #define WM9090_IN2_CLAMP_MASK 0x0001 /* IN2_CLAMP */
187 #define WM9090_IN2_CLAMP_SHIFT 0 /* IN2_CLAMP */
191 * R24 (0x18) - IN1 Line Input A Volume
193 #define WM9090_IN1_VU 0x0100 /* IN1_VU */
194 #define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */
197 #define WM9090_IN1A_MUTE 0x0080 /* IN1A_MUTE */
198 #define WM9090_IN1A_MUTE_MASK 0x0080 /* IN1A_MUTE */
201 #define WM9090_IN1A_ZC 0x0040 /* IN1A_ZC */
202 #define WM9090_IN1A_ZC_MASK 0x0040 /* IN1A_ZC */
205 #define WM9090_IN1A_VOL_MASK 0x0007 /* IN1A_VOL - [2:0] */
206 #define WM9090_IN1A_VOL_SHIFT 0 /* IN1A_VOL - [2:0] */
207 #define WM9090_IN1A_VOL_WIDTH 3 /* IN1A_VOL - [2:0] */
210 * R25 (0x19) - IN1 Line Input B Volume
212 #define WM9090_IN1_VU 0x0100 /* IN1_VU */
213 #define WM9090_IN1_VU_MASK 0x0100 /* IN1_VU */
216 #define WM9090_IN1B_MUTE 0x0080 /* IN1B_MUTE */
217 #define WM9090_IN1B_MUTE_MASK 0x0080 /* IN1B_MUTE */
220 #define WM9090_IN1B_ZC 0x0040 /* IN1B_ZC */
221 #define WM9090_IN1B_ZC_MASK 0x0040 /* IN1B_ZC */
224 #define WM9090_IN1B_VOL_MASK 0x0007 /* IN1B_VOL - [2:0] */
225 #define WM9090_IN1B_VOL_SHIFT 0 /* IN1B_VOL - [2:0] */
226 #define WM9090_IN1B_VOL_WIDTH 3 /* IN1B_VOL - [2:0] */
229 * R26 (0x1A) - IN2 Line Input A Volume
231 #define WM9090_IN2_VU 0x0100 /* IN2_VU */
232 #define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */
235 #define WM9090_IN2A_MUTE 0x0080 /* IN2A_MUTE */
236 #define WM9090_IN2A_MUTE_MASK 0x0080 /* IN2A_MUTE */
239 #define WM9090_IN2A_ZC 0x0040 /* IN2A_ZC */
240 #define WM9090_IN2A_ZC_MASK 0x0040 /* IN2A_ZC */
243 #define WM9090_IN2A_VOL_MASK 0x0007 /* IN2A_VOL - [2:0] */
244 #define WM9090_IN2A_VOL_SHIFT 0 /* IN2A_VOL - [2:0] */
245 #define WM9090_IN2A_VOL_WIDTH 3 /* IN2A_VOL - [2:0] */
248 * R27 (0x1B) - IN2 Line Input B Volume
250 #define WM9090_IN2_VU 0x0100 /* IN2_VU */
251 #define WM9090_IN2_VU_MASK 0x0100 /* IN2_VU */
254 #define WM9090_IN2B_MUTE 0x0080 /* IN2B_MUTE */
255 #define WM9090_IN2B_MUTE_MASK 0x0080 /* IN2B_MUTE */
258 #define WM9090_IN2B_ZC 0x0040 /* IN2B_ZC */
259 #define WM9090_IN2B_ZC_MASK 0x0040 /* IN2B_ZC */
262 #define WM9090_IN2B_VOL_MASK 0x0007 /* IN2B_VOL - [2:0] */
263 #define WM9090_IN2B_VOL_SHIFT 0 /* IN2B_VOL - [2:0] */
264 #define WM9090_IN2B_VOL_WIDTH 3 /* IN2B_VOL - [2:0] */
267 * R28 (0x1C) - Left Output Volume
269 #define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */
270 #define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
273 #define WM9090_HPOUT1L_ZC 0x0080 /* HPOUT1L_ZC */
274 #define WM9090_HPOUT1L_ZC_MASK 0x0080 /* HPOUT1L_ZC */
277 #define WM9090_HPOUT1L_MUTE 0x0040 /* HPOUT1L_MUTE */
278 #define WM9090_HPOUT1L_MUTE_MASK 0x0040 /* HPOUT1L_MUTE */
281 #define WM9090_HPOUT1L_VOL_MASK 0x003F /* HPOUT1L_VOL - [5:0] */
282 #define WM9090_HPOUT1L_VOL_SHIFT 0 /* HPOUT1L_VOL - [5:0] */
283 #define WM9090_HPOUT1L_VOL_WIDTH 6 /* HPOUT1L_VOL - [5:0] */
286 * R29 (0x1D) - Right Output Volume
288 #define WM9090_HPOUT1_VU 0x0100 /* HPOUT1_VU */
289 #define WM9090_HPOUT1_VU_MASK 0x0100 /* HPOUT1_VU */
292 #define WM9090_HPOUT1R_ZC 0x0080 /* HPOUT1R_ZC */
293 #define WM9090_HPOUT1R_ZC_MASK 0x0080 /* HPOUT1R_ZC */
296 #define WM9090_HPOUT1R_MUTE 0x0040 /* HPOUT1R_MUTE */
297 #define WM9090_HPOUT1R_MUTE_MASK 0x0040 /* HPOUT1R_MUTE */
300 #define WM9090_HPOUT1R_VOL_MASK 0x003F /* HPOUT1R_VOL - [5:0] */
301 #define WM9090_HPOUT1R_VOL_SHIFT 0 /* HPOUT1R_VOL - [5:0] */
302 #define WM9090_HPOUT1R_VOL_WIDTH 6 /* HPOUT1R_VOL - [5:0] */
305 * R34 (0x22) - SPKMIXL Attenuation
307 #define WM9090_SPKMIX_MUTE 0x0100 /* SPKMIX_MUTE */
308 #define WM9090_SPKMIX_MUTE_MASK 0x0100 /* SPKMIX_MUTE */
311 #define WM9090_IN1A_SPKMIX_VOL_MASK 0x00C0 /* IN1A_SPKMIX_VOL - [7:6] */
314 #define WM9090_IN1B_SPKMIX_VOL_MASK 0x0030 /* IN1B_SPKMIX_VOL - [5:4] */
317 #define WM9090_IN2A_SPKMIX_VOL_MASK 0x000C /* IN2A_SPKMIX_VOL - [3:2] */
320 #define WM9090_IN2B_SPKMIX_VOL_MASK 0x0003 /* IN2B_SPKMIX_VOL - [1:0] */
321 #define WM9090_IN2B_SPKMIX_VOL_SHIFT 0 /* IN2B_SPKMIX_VOL - [1:0] */
322 #define WM9090_IN2B_SPKMIX_VOL_WIDTH 2 /* IN2B_SPKMIX_VOL - [1:0] */
325 * R36 (0x24) - SPKOUT Mixers
327 #define WM9090_SPKMIXL_TO_SPKOUTL 0x0010 /* SPKMIXL_TO_SPKOUTL */
328 #define WM9090_SPKMIXL_TO_SPKOUTL_MASK 0x0010 /* SPKMIXL_TO_SPKOUTL */
333 * R37 (0x25) - ClassD3
335 #define WM9090_SPKOUTL_BOOST_MASK 0x0038 /* SPKOUTL_BOOST - [5:3] */
340 * R38 (0x26) - Speaker Volume Left
342 #define WM9090_SPKOUT_VU 0x0100 /* SPKOUT_VU */
343 #define WM9090_SPKOUT_VU_MASK 0x0100 /* SPKOUT_VU */
346 #define WM9090_SPKOUTL_ZC 0x0080 /* SPKOUTL_ZC */
347 #define WM9090_SPKOUTL_ZC_MASK 0x0080 /* SPKOUTL_ZC */
350 #define WM9090_SPKOUTL_MUTE 0x0040 /* SPKOUTL_MUTE */
351 #define WM9090_SPKOUTL_MUTE_MASK 0x0040 /* SPKOUTL_MUTE */
354 #define WM9090_SPKOUTL_VOL_MASK 0x003F /* SPKOUTL_VOL - [5:0] */
355 #define WM9090_SPKOUTL_VOL_SHIFT 0 /* SPKOUTL_VOL - [5:0] */
356 #define WM9090_SPKOUTL_VOL_WIDTH 6 /* SPKOUTL_VOL - [5:0] */
359 * R45 (0x2D) - Output Mixer1
361 #define WM9090_IN1A_TO_MIXOUTL 0x0040 /* IN1A_TO_MIXOUTL */
362 #define WM9090_IN1A_TO_MIXOUTL_MASK 0x0040 /* IN1A_TO_MIXOUTL */
365 #define WM9090_IN2A_TO_MIXOUTL 0x0004 /* IN2A_TO_MIXOUTL */
366 #define WM9090_IN2A_TO_MIXOUTL_MASK 0x0004 /* IN2A_TO_MIXOUTL */
371 * R46 (0x2E) - Output Mixer2
373 #define WM9090_IN1A_TO_MIXOUTR 0x0040 /* IN1A_TO_MIXOUTR */
374 #define WM9090_IN1A_TO_MIXOUTR_MASK 0x0040 /* IN1A_TO_MIXOUTR */
377 #define WM9090_IN1B_TO_MIXOUTR 0x0010 /* IN1B_TO_MIXOUTR */
378 #define WM9090_IN1B_TO_MIXOUTR_MASK 0x0010 /* IN1B_TO_MIXOUTR */
381 #define WM9090_IN2A_TO_MIXOUTR 0x0004 /* IN2A_TO_MIXOUTR */
382 #define WM9090_IN2A_TO_MIXOUTR_MASK 0x0004 /* IN2A_TO_MIXOUTR */
385 #define WM9090_IN2B_TO_MIXOUTR 0x0001 /* IN2B_TO_MIXOUTR */
386 #define WM9090_IN2B_TO_MIXOUTR_MASK 0x0001 /* IN2B_TO_MIXOUTR */
387 #define WM9090_IN2B_TO_MIXOUTR_SHIFT 0 /* IN2B_TO_MIXOUTR */
391 * R47 (0x2F) - Output Mixer3
393 #define WM9090_MIXOUTL_MUTE 0x0100 /* MIXOUTL_MUTE */
394 #define WM9090_MIXOUTL_MUTE_MASK 0x0100 /* MIXOUTL_MUTE */
397 #define WM9090_IN1A_MIXOUTL_VOL_MASK 0x00C0 /* IN1A_MIXOUTL_VOL - [7:6] */
400 #define WM9090_IN2A_MIXOUTL_VOL_MASK 0x000C /* IN2A_MIXOUTL_VOL - [3:2] */
405 * R48 (0x30) - Output Mixer4
407 #define WM9090_MIXOUTR_MUTE 0x0100 /* MIXOUTR_MUTE */
408 #define WM9090_MIXOUTR_MUTE_MASK 0x0100 /* MIXOUTR_MUTE */
411 #define WM9090_IN1A_MIXOUTR_VOL_MASK 0x00C0 /* IN1A_MIXOUTR_VOL - [7:6] */
414 #define WM9090_IN1B_MIXOUTR_VOL_MASK 0x0030 /* IN1B_MIXOUTR_VOL - [5:4] */
417 #define WM9090_IN2A_MIXOUTR_VOL_MASK 0x000C /* IN2A_MIXOUTR_VOL - [3:2] */
420 #define WM9090_IN2B_MIXOUTR_VOL_MASK 0x0003 /* IN2B_MIXOUTR_VOL - [1:0] */
421 #define WM9090_IN2B_MIXOUTR_VOL_SHIFT 0 /* IN2B_MIXOUTR_VOL - [1:0] */
422 #define WM9090_IN2B_MIXOUTR_VOL_WIDTH 2 /* IN2B_MIXOUTR_VOL - [1:0] */
425 * R54 (0x36) - Speaker Mixer
427 #define WM9090_IN1A_TO_SPKMIX 0x0040 /* IN1A_TO_SPKMIX */
428 #define WM9090_IN1A_TO_SPKMIX_MASK 0x0040 /* IN1A_TO_SPKMIX */
431 #define WM9090_IN1B_TO_SPKMIX 0x0010 /* IN1B_TO_SPKMIX */
432 #define WM9090_IN1B_TO_SPKMIX_MASK 0x0010 /* IN1B_TO_SPKMIX */
435 #define WM9090_IN2A_TO_SPKMIX 0x0004 /* IN2A_TO_SPKMIX */
436 #define WM9090_IN2A_TO_SPKMIX_MASK 0x0004 /* IN2A_TO_SPKMIX */
439 #define WM9090_IN2B_TO_SPKMIX 0x0001 /* IN2B_TO_SPKMIX */
440 #define WM9090_IN2B_TO_SPKMIX_MASK 0x0001 /* IN2B_TO_SPKMIX */
441 #define WM9090_IN2B_TO_SPKMIX_SHIFT 0 /* IN2B_TO_SPKMIX */
445 * R57 (0x39) - AntiPOP2
447 #define WM9090_VMID_BUF_ENA 0x0008 /* VMID_BUF_ENA */
448 #define WM9090_VMID_BUF_ENA_MASK 0x0008 /* VMID_BUF_ENA */
451 #define WM9090_VMID_ENA 0x0001 /* VMID_ENA */
452 #define WM9090_VMID_ENA_MASK 0x0001 /* VMID_ENA */
453 #define WM9090_VMID_ENA_SHIFT 0 /* VMID_ENA */
457 * R70 (0x46) - Write Sequencer 0
459 #define WM9090_WSEQ_ENA 0x0100 /* WSEQ_ENA */
460 #define WM9090_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */
463 #define WM9090_WSEQ_WRITE_INDEX_MASK 0x000F /* WSEQ_WRITE_INDEX - [3:0] */
464 #define WM9090_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [3:0] */
465 #define WM9090_WSEQ_WRITE_INDEX_WIDTH 4 /* WSEQ_WRITE_INDEX - [3:0] */
468 * R71 (0x47) - Write Sequencer 1
470 #define WM9090_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */
473 #define WM9090_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */
476 #define WM9090_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */
477 #define WM9090_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */
478 #define WM9090_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */
481 * R72 (0x48) - Write Sequencer 2
483 #define WM9090_WSEQ_EOS 0x4000 /* WSEQ_EOS */
484 #define WM9090_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */
487 #define WM9090_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */
490 #define WM9090_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */
491 #define WM9090_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */
492 #define WM9090_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */
495 * R73 (0x49) - Write Sequencer 3
497 #define WM9090_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */
498 #define WM9090_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */
501 #define WM9090_WSEQ_START 0x0100 /* WSEQ_START */
502 #define WM9090_WSEQ_START_MASK 0x0100 /* WSEQ_START */
505 #define WM9090_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */
506 #define WM9090_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */
507 #define WM9090_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */
510 * R74 (0x4A) - Write Sequencer 4
512 #define WM9090_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */
513 #define WM9090_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */
514 #define WM9090_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */
518 * R75 (0x4B) - Write Sequencer 5
520 #define WM9090_WSEQ_CURRENT_INDEX_MASK 0x003F /* WSEQ_CURRENT_INDEX - [5:0] */
521 #define WM9090_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [5:0] */
522 #define WM9090_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [5:0] */
525 * R76 (0x4C) - Charge Pump 1
527 #define WM9090_CP_ENA 0x8000 /* CP_ENA */
528 #define WM9090_CP_ENA_MASK 0x8000 /* CP_ENA */
533 * R84 (0x54) - DC Servo 0
535 #define WM9090_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */
536 #define WM9090_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */
539 #define WM9090_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */
540 #define WM9090_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */
543 #define WM9090_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */
544 #define WM9090_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */
547 #define WM9090_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */
548 #define WM9090_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */
551 #define WM9090_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */
552 #define WM9090_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */
555 #define WM9090_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */
556 #define WM9090_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */
559 #define WM9090_DCS_TRIG_DAC_WR_1 0x0008 /* DCS_TRIG_DAC_WR_1 */
560 #define WM9090_DCS_TRIG_DAC_WR_1_MASK 0x0008 /* DCS_TRIG_DAC_WR_1 */
563 #define WM9090_DCS_TRIG_DAC_WR_0 0x0004 /* DCS_TRIG_DAC_WR_0 */
564 #define WM9090_DCS_TRIG_DAC_WR_0_MASK 0x0004 /* DCS_TRIG_DAC_WR_0 */
567 #define WM9090_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */
568 #define WM9090_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */
571 #define WM9090_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */
572 #define WM9090_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */
573 #define WM9090_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */
577 * R85 (0x55) - DC Servo 1
579 #define WM9090_DCS_SERIES_NO_01_MASK 0x0FE0 /* DCS_SERIES_NO_01 - [11:5] */
582 #define WM9090_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */
583 #define WM9090_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */
584 #define WM9090_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */
587 * R87 (0x57) - DC Servo 3
589 #define WM9090_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */
592 #define WM9090_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */
593 #define WM9090_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */
594 #define WM9090_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */
597 * R88 (0x58) - DC Servo Readback 0
599 #define WM9090_DCS_CAL_COMPLETE_MASK 0x0300 /* DCS_CAL_COMPLETE - [9:8] */
602 #define WM9090_DCS_DAC_WR_COMPLETE_MASK 0x0030 /* DCS_DAC_WR_COMPLETE - [5:4] */
605 #define WM9090_DCS_STARTUP_COMPLETE_MASK 0x0003 /* DCS_STARTUP_COMPLETE - [1:0] */
606 #define WM9090_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [1:0] */
607 #define WM9090_DCS_STARTUP_COMPLETE_WIDTH 2 /* DCS_STARTUP_COMPLETE - [1:0] */
610 * R89 (0x59) - DC Servo Readback 1
612 #define WM9090_DCS_DAC_WR_VAL_1_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_1_RD - [7:0] */
613 #define WM9090_DCS_DAC_WR_VAL_1_RD_SHIFT 0 /* DCS_DAC_WR_VAL_1_RD - [7:0] */
614 #define WM9090_DCS_DAC_WR_VAL_1_RD_WIDTH 8 /* DCS_DAC_WR_VAL_1_RD - [7:0] */
617 * R90 (0x5A) - DC Servo Readback 2
619 #define WM9090_DCS_DAC_WR_VAL_0_RD_MASK 0x00FF /* DCS_DAC_WR_VAL_0_RD - [7:0] */
620 #define WM9090_DCS_DAC_WR_VAL_0_RD_SHIFT 0 /* DCS_DAC_WR_VAL_0_RD - [7:0] */
621 #define WM9090_DCS_DAC_WR_VAL_0_RD_WIDTH 8 /* DCS_DAC_WR_VAL_0_RD - [7:0] */
624 * R96 (0x60) - Analogue HP 0
626 #define WM9090_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
627 #define WM9090_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
630 #define WM9090_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */
631 #define WM9090_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */
634 #define WM9090_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */
635 #define WM9090_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */
638 #define WM9090_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */
639 #define WM9090_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */
642 #define WM9090_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */
643 #define WM9090_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */
646 #define WM9090_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */
647 #define WM9090_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */
652 * R98 (0x62) - AGC Control 0
654 #define WM9090_AGC_CLIP_ENA 0x8000 /* AGC_CLIP_ENA */
655 #define WM9090_AGC_CLIP_ENA_MASK 0x8000 /* AGC_CLIP_ENA */
658 #define WM9090_AGC_CLIP_THR_MASK 0x0F00 /* AGC_CLIP_THR - [11:8] */
661 #define WM9090_AGC_CLIP_ATK_MASK 0x0070 /* AGC_CLIP_ATK - [6:4] */
664 #define WM9090_AGC_CLIP_DCY_MASK 0x0007 /* AGC_CLIP_DCY - [2:0] */
665 #define WM9090_AGC_CLIP_DCY_SHIFT 0 /* AGC_CLIP_DCY - [2:0] */
666 #define WM9090_AGC_CLIP_DCY_WIDTH 3 /* AGC_CLIP_DCY - [2:0] */
669 * R99 (0x63) - AGC Control 1
671 #define WM9090_AGC_PWR_ENA 0x8000 /* AGC_PWR_ENA */
672 #define WM9090_AGC_PWR_ENA_MASK 0x8000 /* AGC_PWR_ENA */
675 #define WM9090_AGC_PWR_AVG 0x1000 /* AGC_PWR_AVG */
676 #define WM9090_AGC_PWR_AVG_MASK 0x1000 /* AGC_PWR_AVG */
679 #define WM9090_AGC_PWR_THR_MASK 0x0F00 /* AGC_PWR_THR - [11:8] */
682 #define WM9090_AGC_PWR_ATK_MASK 0x0070 /* AGC_PWR_ATK - [6:4] */
685 #define WM9090_AGC_PWR_DCY_MASK 0x0007 /* AGC_PWR_DCY - [2:0] */
686 #define WM9090_AGC_PWR_DCY_SHIFT 0 /* AGC_PWR_DCY - [2:0] */
687 #define WM9090_AGC_PWR_DCY_WIDTH 3 /* AGC_PWR_DCY - [2:0] */
690 * R100 (0x64) - AGC Control 2
692 #define WM9090_AGC_RAMP 0x0100 /* AGC_RAMP */
693 #define WM9090_AGC_RAMP_MASK 0x0100 /* AGC_RAMP */
696 #define WM9090_AGC_MINGAIN_MASK 0x003F /* AGC_MINGAIN - [5:0] */
697 #define WM9090_AGC_MINGAIN_SHIFT 0 /* AGC_MINGAIN - [5:0] */
698 #define WM9090_AGC_MINGAIN_WIDTH 6 /* AGC_MINGAIN - [5:0] */