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/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
Dtegra124-nyan-big-emc.dtsi263 0x40040001 /* MC_EMEM_ARB_CFG */
264 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
265 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
266 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
267 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
268 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
269 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
270 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
271 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
272 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
[all …]
/linux-6.12.1/drivers/cpufreq/
Dpowernow-k8.h43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
/linux-6.12.1/include/sound/
Dcs35l56.h17 #define CS35L56_DEVID 0x0000000
18 #define CS35L56_REVID 0x0000004
19 #define CS35L56_RELID 0x000000C
20 #define CS35L56_OTPID 0x0000010
21 #define CS35L56_SFT_RESET 0x0000020
22 #define CS35L56_GLOBAL_ENABLES 0x0002014
23 #define CS35L56_BLOCK_ENABLES 0x0002018
24 #define CS35L56_BLOCK_ENABLES2 0x000201C
25 #define CS35L56_REFCLK_INPUT 0x0002C04
26 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C
[all …]
/linux-6.12.1/include/linux/ssb/
Dssb_driver_extif.h24 #define SSB_EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
25 #define SSB_EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
26 #define SSB_EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
27 #define SSB_EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
47 #define SSB_EXTIF_CTL 0x0000
48 #define SSB_EXTIF_CTL_UARTEN (1 << 0) /* UART enable */
49 #define SSB_EXTIF_EXTSTAT 0x0004
50 #define SSB_EXTIF_EXTSTAT_EMODE (1 << 0) /* Endian mode (ro) */
53 #define SSB_EXTIF_PCMCIA_CFG 0x0010
54 #define SSB_EXTIF_PCMCIA_MEMWAIT 0x0014
[all …]
/linux-6.12.1/drivers/media/rc/img-ir/
Dimg-ir.h20 #define IMG_IR_CONTROL 0x00
21 #define IMG_IR_STATUS 0x04
22 #define IMG_IR_DATA_LW 0x08
23 #define IMG_IR_DATA_UP 0x0c
24 #define IMG_IR_LEAD_SYMB_TIMING 0x10
25 #define IMG_IR_S00_SYMB_TIMING 0x14
26 #define IMG_IR_S01_SYMB_TIMING 0x18
27 #define IMG_IR_S10_SYMB_TIMING 0x1c
28 #define IMG_IR_S11_SYMB_TIMING 0x20
29 #define IMG_IR_FREE_SYMB_TIMING 0x24
[all …]
/linux-6.12.1/arch/powerpc/include/asm/nohash/32/
Dmmu-44x.h10 #define PPC44x_MMUCR_TID 0x000000ff
11 #define PPC44x_MMUCR_STS 0x00010000
13 #define PPC44x_TLB_PAGEID 0
18 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
19 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
20 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
21 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
22 #define PPC44x_TLB_4K 0x00000010
23 #define PPC44x_TLB_16K 0x00000020
24 #define PPC44x_TLB_64K 0x00000030
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
Dgk104.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); in gk104_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); in gk104_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); in gk104_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); in gk104_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); in gk104_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); in gk104_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); in gk104_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); in gk104_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); in gk104_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x120058); in gk104_privring_intr()
[all …]
Dgf100.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_privring_intr()
[all …]
Dgk20a.c29 nvkm_mask(device, 0x137250, 0x3f, 0); in gk20a_privring_init_privring_ring()
31 nvkm_mask(device, 0x000200, 0x20, 0); in gk20a_privring_init_privring_ring()
33 nvkm_mask(device, 0x000200, 0x20, 0x20); in gk20a_privring_init_privring_ring()
35 nvkm_wr32(device, 0x12004c, 0x4); in gk20a_privring_init_privring_ring()
36 nvkm_wr32(device, 0x122204, 0x2); in gk20a_privring_init_privring_ring()
37 nvkm_rd32(device, 0x122204); in gk20a_privring_init_privring_ring()
43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_privring_init_privring_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_privring_init_privring_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_privring_init_privring_ring()
52 u32 status0 = nvkm_rd32(device, 0x120058); in gk20a_privring_intr()
[all …]
/linux-6.12.1/include/linux/bcma/
Dbcma_driver_mips.h5 #define BCMA_MIPS_IPSFLAG 0x0F08
7 #define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
8 #define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
10 #define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
13 #define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
16 #define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
20 #define BCMA_MIPS_MIPS74K_CORECTL 0x0000
21 #define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
22 #define BCMA_MIPS_MIPS74K_BIST 0x000C
23 #define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/abi/
Dgsc_pxp_commands_abi.h14 #define PXP_APIVER(x, y) (((x) & 0xFFFF) << 16 | ((y) & 0xFFFF))
22 PXP_STATUS_SUCCESS = 0x0,
23 PXP_STATUS_ERROR_API_VERSION = 0x1002,
24 PXP_STATUS_NOT_READY = 0x100e,
25 PXP_STATUS_PLATFCONFIG_KF1_NOVERIF = 0x101a,
26 PXP_STATUS_PLATFCONFIG_KF1_BAD = 0x101f,
27 PXP_STATUS_OP_NOT_PERMITTED = 0x4013
37 #define PXP_CMDHDR_EXTDATA_SESSION_VALID GENMASK(0, 0)
45 #define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */
/linux-6.12.1/drivers/net/wireless/realtek/rtw89/
Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/pxp/
Dintel_pxp_cmd_interface_43.h13 #define PXP43_CMDID_START_HUC_AUTH 0x0000003A
14 #define PXP43_CMDID_NEW_HUC_AUTH 0x0000003F /* MTL+ */
15 #define PXP43_CMDID_INIT_SESSION 0x00000036
45 #define PXP43_INIT_SESSION_VALID BIT(0)
49 #define PXP43_INIT_SESSION_PROTECTION_ARB 0x2
/linux-6.12.1/drivers/video/fbdev/
Di740_reg.h37 #define XRX 0x3D6
38 #define MRX 0x3D2
41 #define DACMASK 0x3C6
42 #define DACSTATE 0x3C7
43 #define DACRX 0x3C7
44 #define DACWX 0x3C8
45 #define DACDATA 0x3C9
48 #define START_ADDR_HI 0x0C
49 #define START_ADDR_LO 0x0D
50 #define VERT_SYNC_END 0x11
[all …]
/linux-6.12.1/drivers/net/ethernet/renesas/
Dravb.h39 #define RAVB_TXTSTAMP_VALID 0x00000001 /* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED 0x00000010 /* Enable TX timestamping */
42 #define RAVB_RXTSTAMP_VALID 0x00000001 /* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE 0x00000006 /* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL 0x00000006
46 #define RAVB_RXTSTAMP_ENABLED 0x00000010 /* Enable RX timestamping */
50 CCC = 0x0000,
51 DBAT = 0x0004,
52 DLR = 0x0008,
[all …]
/linux-6.12.1/drivers/media/pci/cx88/
Dcx88-tvaudio.c52 "Radio deemphasis time constant, 0=None, 1=50us (elsewhere), 2=75us (USA)");
58 } while (0)
96 for (i = 0; l[i].reg; i++) { in set_audio_registers()
120 cx_write(AUD_INIT_LD, 0x0001); in set_audio_start()
121 cx_write(AUD_SOFT_RESET, 0x0001); in set_audio_start()
130 cx_write(AUD_RATE_THRES_DMD, 0x000000C0); in set_audio_finish()
142 cx_write(AUD_I2SCNTL, 0); in set_audio_finish()
143 /* cx_write(AUD_APB_IN_RATE_ADJ, 0); */ in set_audio_finish()
151 cx_write(AUD_SOFT_RESET, 0x0000); in set_audio_finish()
166 {AUD_AFE_12DB_EN, 0x00000001}, in set_audio_standard_BTSC()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dgk104.c54 if (!(ssrc & 0x00000100)) in read_vco()
55 return read_pll(clk, 0x00e800); in read_vco()
56 return read_pll(clk, 0x00e820); in read_vco()
63 u32 ctrl = nvkm_rd32(device, pll + 0x00); in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll()
65 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
66 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
67 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
69 u16 fN = 0xf000; in read_pll()
71 if (!(ctrl & 0x00000001)) in read_pll()
[all …]
/linux-6.12.1/tools/power/cpupower/debug/i386/
Dpowernow-k8-decode.c22 #define MSR_FIDVID_STATUS 0xc0010042
24 #define MSR_S_HI_CURRENT_VID 0x0000001f
25 #define MSR_S_LO_CURRENT_FID 0x0000003f
30 uint64_t msr = 0; in get_fidvid()
40 if (fd < 0) in get_fidvid()
46 *fid = ((uint32_t )(msr & 0xffffffffull)) & MSR_S_LO_CURRENT_FID; in get_fidvid()
47 *vid = ((uint32_t )(msr>>32 & 0xffffffffull)) & MSR_S_HI_CURRENT_VID; in get_fidvid()
48 err = 0; in get_fidvid()
75 cpu = 0; in main()
77 cpu = strtoul(argv[1], NULL, 0); in main()
[all …]
/linux-6.12.1/drivers/dma/ptdma/
Dptdma-debugfs.c18 #define RI_VERSION_NUM 0x0000003F
20 #define RI_NUM_VQM 0x00078000
39 return 0; in pt_debugfs_info_show()
52 return 0; in pt_debugfs_stats_show()
61 return 0; in pt_debugfs_queue_show()
65 regval = ioread32(cmd_q->reg_control + 0x000C); in pt_debugfs_queue_show()
78 return 0; in pt_debugfs_queue_show()
/linux-6.12.1/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_internal.h21 #define HW_ATL2_MAC_UC 0U
27 #define HW_ATL2_INT_MASK (0xFFFFFFFFU)
37 #define HW_ATL2_INTR_MODER_MAX 0x1FF
38 #define HW_ATL2_INTR_MODER_MIN 0xFF
48 #define HW_ATL2_FW_SM_ACT_RSLVR 0x3U
50 #define HW_ATL2_RPF_TAG_UC_OFFSET 0x0
51 #define HW_ATL2_RPF_TAG_ALLMC_OFFSET 0x6
52 #define HW_ATL2_RPF_TAG_ET_OFFSET 0x7
53 #define HW_ATL2_RPF_TAG_VLAN_OFFSET 0xA
54 #define HW_ATL2_RPF_TAG_UNTAG_OFFSET 0xE
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dinst.h25 #define I_JTARGET_SFT 0
26 #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
29 #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
32 #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
34 #define I_IMM_SFT 0
35 #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
36 #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
39 #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
42 #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
45 #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
[all …]
/linux-6.12.1/drivers/gpu/drm/mcde/
Dmcde_drm.h13 #define MCDE_CR 0x00000000
14 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_SHIFT 0
15 #define MCDE_CR_IFIFOEMPTYLINECOUNT_V422_MASK 0x0000003F
22 #define MCDE_CONF0 0x00000004
23 #define MCDE_CONF0_SYNCMUX0 BIT(0)
32 #define MCDE_CONF0_IFIFOCTRLWTRMRKLVL_MASK 0x00007000
34 #define MCDE_CONF0_OUTMUX0_MASK 0x00070000
36 #define MCDE_CONF0_OUTMUX1_MASK 0x00380000
38 #define MCDE_CONF0_OUTMUX2_MASK 0x01C00000
40 #define MCDE_CONF0_OUTMUX3_MASK 0x0E000000
[all …]

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