Lines Matching +full:0 +full:x0000003f
54 if (!(ssrc & 0x00000100)) in read_vco()
55 return read_pll(clk, 0x00e800); in read_vco()
56 return read_pll(clk, 0x00e820); in read_vco()
63 u32 ctrl = nvkm_rd32(device, pll + 0x00); in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll()
65 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
66 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
67 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
69 u16 fN = 0xf000; in read_pll()
71 if (!(ctrl & 0x00000001)) in read_pll()
72 return 0; in read_pll()
75 case 0x00e800: in read_pll()
76 case 0x00e820: in read_pll()
80 case 0x132000: in read_pll()
81 sclk = read_pll(clk, 0x132020); in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
84 case 0x132020: in read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); in read_pll()
86 fN = nvkm_rd32(device, pll + 0x10) >> 16; in read_pll()
88 case 0x137000: in read_pll()
89 case 0x137020: in read_pll()
90 case 0x137040: in read_pll()
91 case 0x1370e0: in read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); in read_pll()
95 return 0; in read_pll()
98 if (P == 0) in read_pll()
112 switch (ssrc & 0x00000003) { in read_div()
113 case 0: in read_div()
114 if ((ssrc & 0x00030000) != 0x00030000) in read_div()
120 if (sctl & 0x80000000) { in read_div()
122 u32 sdiv = (sctl & 0x0000003f) + 2; in read_div()
128 return 0; in read_div()
136 switch (nvkm_rd32(device, 0x1373f4) & 0x0000000f) { in read_mem()
137 case 1: return read_pll(clk, 0x132020); in read_mem()
138 case 2: return read_pll(clk, 0x132000); in read_mem()
140 return 0; in read_mem()
148 u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); in read_clk()
152 u32 ssel = nvkm_rd32(device, 0x137100); in read_clk()
154 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); in read_clk()
157 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
158 sdiv = 0; in read_clk()
161 u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04)); in read_clk()
162 if ((ssrc & 0x00000003) == 0x00000003) { in read_clk()
163 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
164 if (ssrc & 0x00000100) { in read_clk()
165 if (ssrc & 0x40000000) in read_clk()
166 sclk = read_pll(clk, 0x1370e0); in read_clk()
169 sdiv = 0; in read_clk()
172 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
173 sdiv = 0; in read_clk()
177 if (sctl & 0x80000000) { in read_clk()
179 sdiv = ((sctl & 0x00003f00) >> 8) + 2; in read_clk()
181 sdiv = ((sctl & 0x0000003f) >> 0) + 2; in read_clk()
203 return read_clk(clk, 0x00); in gk104_clk_read()
205 return read_clk(clk, 0x01); in gk104_clk_read()
207 return read_clk(clk, 0x02); in gk104_clk_read()
209 return read_clk(clk, 0x07); in gk104_clk_read()
211 return read_clk(clk, 0x08); in gk104_clk_read()
213 return read_clk(clk, 0x0c); in gk104_clk_read()
215 return read_clk(clk, 0x0e); in gk104_clk_read()
239 *ddiv = 0x00000000; in calc_src()
243 *dsrc = 0x00000000; in calc_src()
245 *dsrc |= 0x00030000; in calc_src()
248 *dsrc = 0x00000002; in calc_src()
251 *dsrc = 0x00000003; in calc_src()
256 sclk = read_vco(clk, 0x137160 + (idx * 4)); in calc_src()
270 ret = nvbios_pll_parse(bios, 0x137000 + (idx * 0x20), &limits); in calc_pll()
272 return 0; in calc_pll()
274 limits.refclk = read_div(clk, idx, 0x137120, 0x137140); in calc_pll()
276 return 0; in calc_pll()
279 if (ret <= 0) in calc_pll()
280 return 0; in calc_pll()
292 u32 src0, div0, div1D, div1P = 0; in calc_clk()
293 u32 clk0, clk1 = 0; in calc_clk()
297 return 0; in calc_clk()
304 if (clk0 != freq && (0x0000ff87 & (1 << idx))) { in calc_clk()
316 info->ddiv |= 0x80000000; in calc_clk()
320 info->mdiv |= 0x80000000; in calc_clk()
323 info->ssel = 0; in calc_clk()
327 info->mdiv |= 0x80000000; in calc_clk()
331 info->dsrc = 0x40000100; in calc_clk()
335 return 0; in calc_clk()
344 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || in gk104_clk_calc()
345 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || in gk104_clk_calc()
346 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || in gk104_clk_calc()
347 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || in gk104_clk_calc()
348 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || in gk104_clk_calc()
349 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_pmu)) || in gk104_clk_calc()
350 (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) in gk104_clk_calc()
353 return 0; in gk104_clk_calc()
362 nvkm_mask(device, 0x1371d0 + (idx * 0x04), 0x8000003f, info->ddiv); in gk104_clk_prog_0()
363 nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc); in gk104_clk_prog_0()
371 nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); in gk104_clk_prog_1_0()
373 if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) in gk104_clk_prog_1_0()
382 nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000000); in gk104_clk_prog_1_1()
390 const u32 addr = 0x137000 + (idx * 0x20); in gk104_clk_prog_2()
391 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000000); in gk104_clk_prog_2()
392 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000000); in gk104_clk_prog_2()
394 nvkm_wr32(device, addr + 0x04, info->coef); in gk104_clk_prog_2()
395 nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); in gk104_clk_prog_2()
398 nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); in gk104_clk_prog_2()
400 if (nvkm_rd32(device, addr + 0x00) & 0x00020000) in gk104_clk_prog_2()
403 nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); in gk104_clk_prog_2()
406 nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004); in gk104_clk_prog_2()
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
418 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
427 nvkm_mask(device, 0x137100, (1 << idx), info->ssel); in gk104_clk_prog_4_0()
429 u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); in gk104_clk_prog_4_0()
442 nvkm_mask(device, 0x137160 + (idx * 0x04), 0x40000000, 0x40000000); in gk104_clk_prog_4_1()
443 nvkm_mask(device, 0x137160 + (idx * 0x04), 0x00000100, 0x00000100); in gk104_clk_prog_4_1()
455 { 0x007f, gk104_clk_prog_0 }, /* div programming */ in gk104_clk_prog()
456 { 0x007f, gk104_clk_prog_1_0 }, /* select div mode */ in gk104_clk_prog()
457 { 0xff80, gk104_clk_prog_1_1 }, in gk104_clk_prog()
458 { 0x00ff, gk104_clk_prog_2 }, /* (maybe) program pll */ in gk104_clk_prog()
459 { 0xff80, gk104_clk_prog_3 }, /* final divider */ in gk104_clk_prog()
460 { 0x007f, gk104_clk_prog_4_0 }, /* (maybe) select pll mode */ in gk104_clk_prog()
461 { 0xff80, gk104_clk_prog_4_1 }, in gk104_clk_prog()
465 for (i = 0; i < ARRAY_SIZE(stage); i++) { in gk104_clk_prog()
466 for (j = 0; j < ARRAY_SIZE(clk->eng); j++) { in gk104_clk_prog()
475 return 0; in gk104_clk_prog()
482 memset(clk->eng, 0x00, sizeof(clk->eng)); in gk104_clk_tidy()
492 { nv_clk_src_crystal, 0xff },
493 { nv_clk_src_href , 0xff },
494 { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE | NVKM_CLK_DOM_FLAG_VPSTATE, "core", 2000 },
495 { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE },
496 { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE },
497 { nv_clk_src_mem , 0x03, 0, "memory", 500 },
498 { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE },
499 { nv_clk_src_hubk01 , 0x05 },
500 { nv_clk_src_vdec , 0x06 },
501 { nv_clk_src_pmu , 0x07 },