Lines Matching +full:0 +full:x0000003f
43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
58 #define MSR_FIDVID_CTL 0xc0010041
59 #define MSR_FIDVID_STATUS 0xc0010042
62 #define MSR_C_LO_INIT_FID_VID 0x00010000
63 #define MSR_C_LO_NEW_VID 0x00003f00
64 #define MSR_C_LO_NEW_FID 0x0000003f
68 #define MSR_C_HI_STP_GNT_TO 0x000fffff
71 #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
72 #define MSR_S_LO_MAX_RAMP_VID 0x3f000000
73 #define MSR_S_LO_MAX_FID 0x003f0000
74 #define MSR_S_LO_START_FID 0x00003f00
75 #define MSR_S_LO_CURRENT_FID 0x0000003f
78 #define MSR_S_HI_MIN_WORKING_VID 0x3f000000
79 #define MSR_S_HI_MAX_WORKING_VID 0x003f0000
80 #define MSR_S_HI_START_VID 0x00003f00
81 #define MSR_S_HI_CURRENT_VID 0x0000003f
82 #define MSR_C_HI_STP_GNT_BENIGN 0x00000001
106 #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
107 #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
112 #define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
113 #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
115 #define VID_OFF 0x3f
139 #define PLL_L_MASK 0x7f
141 #define VST_MASK 0x7f
142 #define VID_MASK 0x1f
143 #define FID_MASK 0x1f
144 #define EXT_VID_MASK 0x3f
145 #define EXT_FID_MASK 0x3f
159 #define PSB_VERSION_1_4 0x14