1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_PEER_ENTRY_H_ 27 #define _TX_PEER_ENTRY_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_PEER_ENTRY 18 32 33 #define NUM_OF_QWORDS_TX_PEER_ENTRY 9 34 35 36 struct tx_peer_entry { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t mac_addr_a_31_0 : 32; 39 uint32_t mac_addr_a_47_32 : 16, 40 mac_addr_b_15_0 : 16; 41 uint32_t mac_addr_b_47_16 : 32; 42 uint32_t use_ad_b : 1, 43 strip_insert_vlan_inner : 1, 44 strip_insert_vlan_outer : 1, 45 vlan_llc_mode : 1, 46 key_type : 4, 47 a_msdu_wds_ad3_ad4 : 3, 48 ignore_hard_filters : 1, 49 ignore_soft_filters : 1, 50 epd_output : 1, 51 wds : 1, 52 insert_or_strip : 1, 53 sw_filter_id : 16; 54 uint32_t temporal_key_31_0 : 32; 55 uint32_t temporal_key_63_32 : 32; 56 uint32_t temporal_key_95_64 : 32; 57 uint32_t temporal_key_127_96 : 32; 58 uint32_t temporal_key_159_128 : 32; 59 uint32_t temporal_key_191_160 : 32; 60 uint32_t temporal_key_223_192 : 32; 61 uint32_t temporal_key_255_224 : 32; 62 uint32_t sta_partial_aid : 11, 63 transmit_vif : 4, 64 block_this_user : 1, 65 mesh_amsdu_mode : 2, 66 use_qos_alt_mute_mask : 1, 67 dl_ul_direction : 1, 68 reserved_12 : 12; 69 uint32_t insert_vlan_outer_tci : 16, 70 insert_vlan_inner_tci : 16; 71 uint32_t multi_link_addr_ad1_31_0 : 32; 72 uint32_t multi_link_addr_ad1_47_32 : 16, 73 multi_link_addr_ad2_15_0 : 16; 74 uint32_t multi_link_addr_ad2_47_16 : 32; 75 uint32_t multi_link_addr_crypto_enable : 1, 76 reserved_17a : 15, 77 sw_peer_id : 16; 78 #else 79 uint32_t mac_addr_a_31_0 : 32; 80 uint32_t mac_addr_b_15_0 : 16, 81 mac_addr_a_47_32 : 16; 82 uint32_t mac_addr_b_47_16 : 32; 83 uint32_t sw_filter_id : 16, 84 insert_or_strip : 1, 85 wds : 1, 86 epd_output : 1, 87 ignore_soft_filters : 1, 88 ignore_hard_filters : 1, 89 a_msdu_wds_ad3_ad4 : 3, 90 key_type : 4, 91 vlan_llc_mode : 1, 92 strip_insert_vlan_outer : 1, 93 strip_insert_vlan_inner : 1, 94 use_ad_b : 1; 95 uint32_t temporal_key_31_0 : 32; 96 uint32_t temporal_key_63_32 : 32; 97 uint32_t temporal_key_95_64 : 32; 98 uint32_t temporal_key_127_96 : 32; 99 uint32_t temporal_key_159_128 : 32; 100 uint32_t temporal_key_191_160 : 32; 101 uint32_t temporal_key_223_192 : 32; 102 uint32_t temporal_key_255_224 : 32; 103 uint32_t reserved_12 : 12, 104 dl_ul_direction : 1, 105 use_qos_alt_mute_mask : 1, 106 mesh_amsdu_mode : 2, 107 block_this_user : 1, 108 transmit_vif : 4, 109 sta_partial_aid : 11; 110 uint32_t insert_vlan_inner_tci : 16, 111 insert_vlan_outer_tci : 16; 112 uint32_t multi_link_addr_ad1_31_0 : 32; 113 uint32_t multi_link_addr_ad2_15_0 : 16, 114 multi_link_addr_ad1_47_32 : 16; 115 uint32_t multi_link_addr_ad2_47_16 : 32; 116 uint32_t sw_peer_id : 16, 117 reserved_17a : 15, 118 multi_link_addr_crypto_enable : 1; 119 #endif 120 }; 121 122 123 124 125 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 126 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 127 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 128 #define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff 129 130 131 132 133 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 134 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 135 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 136 #define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 137 138 139 140 141 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 142 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 143 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 144 #define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 145 146 147 148 149 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 150 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 151 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 152 #define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff 153 154 155 156 157 #define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 158 #define TX_PEER_ENTRY_USE_AD_B_LSB 32 159 #define TX_PEER_ENTRY_USE_AD_B_MSB 32 160 #define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 161 162 163 164 165 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 166 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 167 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 168 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 169 170 171 172 173 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 174 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 175 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 176 #define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 177 178 179 180 181 #define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 182 #define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 183 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 184 #define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 185 186 187 188 189 #define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 190 #define TX_PEER_ENTRY_KEY_TYPE_LSB 36 191 #define TX_PEER_ENTRY_KEY_TYPE_MSB 39 192 #define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 193 194 195 196 197 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 198 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 199 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 200 #define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 201 202 203 204 205 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 206 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 207 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 208 #define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 209 210 211 212 213 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 214 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 215 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 216 #define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 217 218 219 220 221 #define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 222 #define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 223 #define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 224 #define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 225 226 227 228 229 #define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 230 #define TX_PEER_ENTRY_WDS_LSB 46 231 #define TX_PEER_ENTRY_WDS_MSB 46 232 #define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 233 234 235 236 237 #define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 238 #define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 239 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 240 #define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 241 242 243 244 245 #define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 246 #define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 247 #define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 248 #define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 249 250 251 252 253 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 254 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 255 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 256 #define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff 257 258 259 260 261 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 262 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 263 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 264 #define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 265 266 267 268 269 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 270 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 271 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 272 #define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff 273 274 275 276 277 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 278 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 279 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 280 #define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 281 282 283 284 285 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 286 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 287 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 288 #define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff 289 290 291 292 293 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 294 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 295 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 296 #define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 297 298 299 300 301 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 302 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 303 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 304 #define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff 305 306 307 308 309 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 310 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 311 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 312 #define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 313 314 315 316 317 #define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 318 #define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 319 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 320 #define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff 321 322 323 324 325 #define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 326 #define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 327 #define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 328 #define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 329 330 331 332 333 #define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 334 #define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 335 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 336 #define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 337 338 339 340 341 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 342 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 343 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 344 #define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 345 346 347 348 349 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 350 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 351 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 352 #define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 353 354 355 356 357 #define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 358 #define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 359 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 360 #define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 361 362 363 364 365 #define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 366 #define TX_PEER_ENTRY_RESERVED_12_LSB 20 367 #define TX_PEER_ENTRY_RESERVED_12_MSB 31 368 #define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 369 370 371 372 373 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 374 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 375 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 376 #define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 377 378 379 380 381 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 382 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 383 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 384 #define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 385 386 387 388 389 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000038 390 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB 0 391 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB 31 392 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff 393 394 395 396 397 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000038 398 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB 32 399 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB 47 400 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 401 402 403 404 405 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000038 406 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB 48 407 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB 63 408 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 409 410 411 412 413 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000040 414 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB 0 415 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB 31 416 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff 417 418 419 420 421 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 422 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 423 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 424 #define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 425 426 427 428 429 #define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 430 #define TX_PEER_ENTRY_RESERVED_17A_LSB 33 431 #define TX_PEER_ENTRY_RESERVED_17A_MSB 47 432 #define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 433 434 435 436 437 #define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 438 #define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 439 #define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 440 #define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 441 442 443 444 #endif 445