1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TX_FES_STATUS_USER_PPDU_H_ 27 #define _TX_FES_STATUS_USER_PPDU_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 32 33 #define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 34 35 36 struct tx_fes_status_user_ppdu { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t underflow_mpdu_count : 9, 39 data_underflow_warning : 2, 40 bw_drop_underflow_warning : 1, 41 qc_eosp_setting : 1, 42 fc_more_data_setting : 1, 43 fc_pwr_mgt_setting : 1, 44 mpdu_tx_count : 9, 45 user_blocked : 1, 46 pre_trig_response_delim_count : 7; 47 uint32_t underflow_byte_count : 16, 48 coex_abort_mpdu_count_valid : 1, 49 coex_abort_mpdu_count : 9, 50 transmitted_tid : 4, 51 txdma_dropped_mpdu_warning : 1, 52 reserved_1 : 1; 53 uint32_t duration : 16, 54 num_eof_delim_added : 16; 55 uint32_t psdu_octet : 24, 56 qos_buf_state : 8; 57 uint32_t num_null_delim_added : 22, 58 reserved_4a : 2, 59 cv_corr_user_valid_in_phy : 1, 60 nss : 3, 61 mcs : 4; 62 uint32_t ht_control : 32; 63 #else 64 uint32_t pre_trig_response_delim_count : 7, 65 user_blocked : 1, 66 mpdu_tx_count : 9, 67 fc_pwr_mgt_setting : 1, 68 fc_more_data_setting : 1, 69 qc_eosp_setting : 1, 70 bw_drop_underflow_warning : 1, 71 data_underflow_warning : 2, 72 underflow_mpdu_count : 9; 73 uint32_t reserved_1 : 1, 74 txdma_dropped_mpdu_warning : 1, 75 transmitted_tid : 4, 76 coex_abort_mpdu_count : 9, 77 coex_abort_mpdu_count_valid : 1, 78 underflow_byte_count : 16; 79 uint32_t num_eof_delim_added : 16, 80 duration : 16; 81 uint32_t qos_buf_state : 8, 82 psdu_octet : 24; 83 uint32_t mcs : 4, 84 nss : 3, 85 cv_corr_user_valid_in_phy : 1, 86 reserved_4a : 2, 87 num_null_delim_added : 22; 88 uint32_t ht_control : 32; 89 #endif 90 }; 91 92 93 94 95 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 96 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 97 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 98 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 99 100 101 102 103 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 104 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 105 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 106 #define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 107 108 109 110 111 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 112 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 113 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 114 #define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 115 116 117 118 119 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 120 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 121 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 122 #define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 123 124 125 126 127 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 128 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 129 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 130 #define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 131 132 133 134 135 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 136 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 137 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 138 #define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 139 140 141 142 143 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 144 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 145 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 146 #define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 147 148 149 150 151 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 152 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 153 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 154 #define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 155 156 157 158 159 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 160 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 161 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 162 #define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 163 164 165 166 167 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 168 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 169 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 170 #define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 171 172 173 174 175 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 176 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 177 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 178 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 179 180 181 182 183 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 184 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 185 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 186 #define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 187 188 189 190 191 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 192 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 193 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 194 #define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 195 196 197 198 199 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 200 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 201 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 202 #define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 203 204 205 206 207 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 208 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 209 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 210 #define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 211 212 213 214 215 #define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 216 #define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 217 #define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 218 #define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff 219 220 221 222 223 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 224 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 225 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 226 #define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 227 228 229 230 231 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 232 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 233 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 234 #define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 235 236 237 238 239 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 240 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 241 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 242 #define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 243 244 245 246 247 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 248 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 249 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 250 #define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff 251 252 253 254 255 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 256 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 257 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 258 #define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 259 260 261 262 263 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 264 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 265 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 266 #define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 267 268 269 270 271 #define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 272 #define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 273 #define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 274 #define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 275 276 277 278 279 #define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 280 #define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 281 #define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 282 #define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 283 284 285 286 287 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 288 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 289 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 290 #define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 291 292 293 294 #endif 295