1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _TCL_STATUS_RING_H_ 27 #define _TCL_STATUS_RING_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 32 33 34 struct tcl_status_ring { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t gse_ctrl : 4, 37 ase_fse_sel : 1, 38 cache_op_res : 2, 39 index_search_en : 1, 40 msdu_cnt_n : 24; 41 uint32_t msdu_byte_cnt_n : 32; 42 uint32_t msdu_timestmp_n : 32; 43 uint32_t cmd_meta_data_31_0 : 32; 44 uint32_t cmd_meta_data_63_32 : 32; 45 uint32_t hash_indx_val : 20, 46 cache_set_num : 4, 47 reserved_5a : 8; 48 uint32_t reserved_6a : 32; 49 uint32_t reserved_7a : 20, 50 ring_id : 8, 51 looping_count : 4; 52 #else 53 uint32_t msdu_cnt_n : 24, 54 index_search_en : 1, 55 cache_op_res : 2, 56 ase_fse_sel : 1, 57 gse_ctrl : 4; 58 uint32_t msdu_byte_cnt_n : 32; 59 uint32_t msdu_timestmp_n : 32; 60 uint32_t cmd_meta_data_31_0 : 32; 61 uint32_t cmd_meta_data_63_32 : 32; 62 uint32_t reserved_5a : 8, 63 cache_set_num : 4, 64 hash_indx_val : 20; 65 uint32_t reserved_6a : 32; 66 uint32_t looping_count : 4, 67 ring_id : 8, 68 reserved_7a : 20; 69 #endif 70 }; 71 72 73 74 75 #define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 76 #define TCL_STATUS_RING_GSE_CTRL_LSB 0 77 #define TCL_STATUS_RING_GSE_CTRL_MSB 3 78 #define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f 79 80 81 82 83 #define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 84 #define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 85 #define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 86 #define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 87 88 89 90 91 #define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 92 #define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 93 #define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 94 #define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 95 96 97 98 99 #define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 100 #define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 101 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 102 #define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 103 104 105 106 107 #define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 108 #define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 109 #define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 110 #define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 111 112 113 114 115 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 116 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 117 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 118 #define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff 119 120 121 122 123 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 124 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 125 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 126 #define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff 127 128 129 130 131 #define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c 132 #define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 133 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 134 #define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff 135 136 137 138 139 #define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 140 #define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 141 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 142 #define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff 143 144 145 146 147 #define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 148 #define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 149 #define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 150 #define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff 151 152 153 154 155 #define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 156 #define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 157 #define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 158 #define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 159 160 161 162 163 #define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 164 #define TCL_STATUS_RING_RESERVED_5A_LSB 24 165 #define TCL_STATUS_RING_RESERVED_5A_MSB 31 166 #define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 167 168 169 170 171 #define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 172 #define TCL_STATUS_RING_RESERVED_6A_LSB 0 173 #define TCL_STATUS_RING_RESERVED_6A_MSB 31 174 #define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff 175 176 177 178 179 #define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c 180 #define TCL_STATUS_RING_RESERVED_7A_LSB 0 181 #define TCL_STATUS_RING_RESERVED_7A_MSB 19 182 #define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff 183 184 185 186 187 #define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c 188 #define TCL_STATUS_RING_RING_ID_LSB 20 189 #define TCL_STATUS_RING_RING_ID_MSB 27 190 #define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 191 192 193 194 195 #define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c 196 #define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 197 #define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 198 #define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 199 200 201 202 #endif 203