1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_TRIG_INFO_H_ 27 #define _RX_TRIG_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_TRIG_INFO 2 32 33 #define NUM_OF_QWORDS_RX_TRIG_INFO 1 34 35 36 struct rx_trig_info { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rx_trigger_frame_type : 2, 39 trigger_resp_type : 3, 40 reserved_0 : 27; 41 uint32_t ppdu_duration : 16, 42 unique_destination_id : 16; 43 #else 44 uint32_t reserved_0 : 27, 45 trigger_resp_type : 3, 46 rx_trigger_frame_type : 2; 47 uint32_t unique_destination_id : 16, 48 ppdu_duration : 16; 49 #endif 50 }; 51 52 53 54 55 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 56 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 57 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 58 #define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 59 60 61 62 63 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 64 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 65 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 66 #define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c 67 68 69 70 71 #define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 72 #define RX_TRIG_INFO_RESERVED_0_LSB 5 73 #define RX_TRIG_INFO_RESERVED_0_MSB 31 74 #define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 75 76 77 78 79 #define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 80 #define RX_TRIG_INFO_PPDU_DURATION_LSB 32 81 #define RX_TRIG_INFO_PPDU_DURATION_MSB 47 82 #define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 83 84 85 86 87 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 88 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 89 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 90 #define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 91 92 93 94 #endif 95