1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RESPONSE_END_STATUS_H_ 27 #define _RESPONSE_END_STATUS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "phytx_abort_request_info.h" 32 #define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 33 34 #define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 35 36 37 struct response_end_status { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t coex_bt_tx_while_wlan_tx : 1, 40 coex_wan_tx_while_wlan_tx : 1, 41 coex_wlan_tx_while_wlan_tx : 1, 42 global_data_underflow_warning : 1, 43 response_transmit_status : 4, 44 phytx_pkt_end_info_valid : 1, 45 phytx_abort_request_info_valid : 1, 46 generated_response : 3, 47 mba_user_count : 7, 48 mba_fake_bitmap_count : 7, 49 coex_based_tx_bw : 3, 50 trig_response_related : 1, 51 dpdtrain_done : 1; 52 struct phytx_abort_request_info phytx_abort_request_info_details; 53 uint16_t cbf_segment_request_mask : 8, 54 cbf_segment_sent_mask : 8; 55 uint32_t underflow_mpdu_count : 9, 56 data_underflow_warning : 2, 57 phy_tx_gain_setting : 8, 58 timing_status : 2, 59 only_null_delim_sent : 1, 60 brp_info_valid : 1, 61 reserved_2a : 9; 62 uint32_t mu_response_bitmap_31_0 : 32; 63 uint32_t mu_response_bitmap_36_32 : 5, 64 reserved_4a : 11, 65 transmit_delay : 16; 66 uint32_t start_of_frame_timestamp_15_0 : 16, 67 start_of_frame_timestamp_31_16 : 16; 68 uint32_t end_of_frame_timestamp_15_0 : 16, 69 end_of_frame_timestamp_31_16 : 16; 70 uint32_t tx_group_delay : 12, 71 reserved_7a : 4, 72 tpc_dbg_info_cmn_15_0 : 16; 73 uint32_t tpc_dbg_info_31_16 : 16, 74 tpc_dbg_info_47_32 : 16; 75 uint32_t tpc_dbg_info_chn1_15_0 : 16, 76 tpc_dbg_info_chn1_31_16 : 16; 77 uint32_t tpc_dbg_info_chn1_47_32 : 16, 78 tpc_dbg_info_chn1_63_48 : 16; 79 uint32_t tpc_dbg_info_chn1_79_64 : 16, 80 tpc_dbg_info_chn2_15_0 : 16; 81 uint32_t tpc_dbg_info_chn2_31_16 : 16, 82 tpc_dbg_info_chn2_47_32 : 16; 83 uint32_t tpc_dbg_info_chn2_63_48 : 16, 84 tpc_dbg_info_chn2_79_64 : 16; 85 uint32_t phytx_tx_end_sw_info_15_0 : 16, 86 phytx_tx_end_sw_info_31_16 : 16; 87 uint32_t phytx_tx_end_sw_info_47_32 : 16, 88 phytx_tx_end_sw_info_63_48 : 16; 89 uint32_t addr1_31_0 : 32; 90 uint32_t addr1_47_32 : 16, 91 addr2_15_0 : 16; 92 uint32_t addr2_47_16 : 32; 93 uint32_t addr3_31_0 : 32; 94 uint32_t addr3_47_32 : 16, 95 ranging : 1, 96 secure : 1, 97 ranging_ftm_frame_sent : 1, 98 reserved_20a : 13; 99 uint32_t tlv64_padding : 32; 100 #else 101 uint32_t dpdtrain_done : 1, 102 trig_response_related : 1, 103 coex_based_tx_bw : 3, 104 mba_fake_bitmap_count : 7, 105 mba_user_count : 7, 106 generated_response : 3, 107 phytx_abort_request_info_valid : 1, 108 phytx_pkt_end_info_valid : 1, 109 response_transmit_status : 4, 110 global_data_underflow_warning : 1, 111 coex_wlan_tx_while_wlan_tx : 1, 112 coex_wan_tx_while_wlan_tx : 1, 113 coex_bt_tx_while_wlan_tx : 1; 114 uint32_t cbf_segment_sent_mask : 8, 115 cbf_segment_request_mask : 8; 116 struct phytx_abort_request_info phytx_abort_request_info_details; 117 uint32_t reserved_2a : 9, 118 brp_info_valid : 1, 119 only_null_delim_sent : 1, 120 timing_status : 2, 121 phy_tx_gain_setting : 8, 122 data_underflow_warning : 2, 123 underflow_mpdu_count : 9; 124 uint32_t mu_response_bitmap_31_0 : 32; 125 uint32_t transmit_delay : 16, 126 reserved_4a : 11, 127 mu_response_bitmap_36_32 : 5; 128 uint32_t start_of_frame_timestamp_31_16 : 16, 129 start_of_frame_timestamp_15_0 : 16; 130 uint32_t end_of_frame_timestamp_31_16 : 16, 131 end_of_frame_timestamp_15_0 : 16; 132 uint32_t tpc_dbg_info_cmn_15_0 : 16, 133 reserved_7a : 4, 134 tx_group_delay : 12; 135 uint32_t tpc_dbg_info_47_32 : 16, 136 tpc_dbg_info_31_16 : 16; 137 uint32_t tpc_dbg_info_chn1_31_16 : 16, 138 tpc_dbg_info_chn1_15_0 : 16; 139 uint32_t tpc_dbg_info_chn1_63_48 : 16, 140 tpc_dbg_info_chn1_47_32 : 16; 141 uint32_t tpc_dbg_info_chn2_15_0 : 16, 142 tpc_dbg_info_chn1_79_64 : 16; 143 uint32_t tpc_dbg_info_chn2_47_32 : 16, 144 tpc_dbg_info_chn2_31_16 : 16; 145 uint32_t tpc_dbg_info_chn2_79_64 : 16, 146 tpc_dbg_info_chn2_63_48 : 16; 147 uint32_t phytx_tx_end_sw_info_31_16 : 16, 148 phytx_tx_end_sw_info_15_0 : 16; 149 uint32_t phytx_tx_end_sw_info_63_48 : 16, 150 phytx_tx_end_sw_info_47_32 : 16; 151 uint32_t addr1_31_0 : 32; 152 uint32_t addr2_15_0 : 16, 153 addr1_47_32 : 16; 154 uint32_t addr2_47_16 : 32; 155 uint32_t addr3_31_0 : 32; 156 uint32_t reserved_20a : 13, 157 ranging_ftm_frame_sent : 1, 158 secure : 1, 159 ranging : 1, 160 addr3_47_32 : 16; 161 uint32_t tlv64_padding : 32; 162 #endif 163 }; 164 165 166 167 168 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 169 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 170 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 171 #define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 172 173 174 175 176 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 177 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 178 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 179 #define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 180 181 182 183 184 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 185 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 186 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 187 #define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 188 189 190 191 192 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 193 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 194 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 195 #define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 196 197 198 199 200 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 201 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 202 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 203 #define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 204 205 206 207 208 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 209 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 210 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 211 #define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 212 213 214 215 216 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 217 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 218 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 219 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 220 221 222 223 224 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 225 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 226 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 227 #define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 228 229 230 231 232 #define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 233 #define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 234 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 235 #define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 236 237 238 239 240 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 241 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 242 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 243 #define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 244 245 246 247 248 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 249 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 250 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 251 #define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 252 253 254 255 256 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 257 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 258 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 259 #define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 260 261 262 263 264 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 265 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 266 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 267 #define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 268 269 270 271 272 273 274 275 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 276 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 277 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 278 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 279 280 281 282 283 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 284 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 285 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 286 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 287 288 289 290 291 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 292 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 293 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 294 #define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 295 296 297 298 299 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 300 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 301 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 302 #define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 303 304 305 306 307 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 308 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 309 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 310 #define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 311 312 313 314 315 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 316 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 317 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 318 #define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff 319 320 321 322 323 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 324 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 325 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 326 #define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 327 328 329 330 331 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 332 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 333 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 334 #define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 335 336 337 338 339 #define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 340 #define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 341 #define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 342 #define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 343 344 345 346 347 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 348 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 349 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 350 #define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 351 352 353 354 355 #define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 356 #define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 357 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 358 #define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 359 360 361 362 363 #define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 364 #define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 365 #define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 366 #define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 367 368 369 370 371 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 372 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 373 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 374 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 375 376 377 378 379 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 380 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 381 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 382 #define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f 383 384 385 386 387 #define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 388 #define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 389 #define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 390 #define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 391 392 393 394 395 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 396 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 397 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 398 #define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 399 400 401 402 403 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 404 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 405 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 406 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 407 408 409 410 411 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 412 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 413 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 414 #define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 415 416 417 418 419 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 420 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 421 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 422 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff 423 424 425 426 427 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 428 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 429 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 430 #define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 431 432 433 434 435 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 436 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 437 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 438 #define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 439 440 441 442 443 #define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 444 #define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 445 #define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 446 #define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 447 448 449 450 451 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 452 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 453 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 454 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 455 456 457 458 459 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 460 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 461 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 462 #define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff 463 464 465 466 467 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 468 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 469 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 470 #define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 471 472 473 474 475 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 476 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 477 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 478 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 479 480 481 482 483 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 484 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 485 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 486 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 487 488 489 490 491 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 492 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 493 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 494 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff 495 496 497 498 499 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 500 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 501 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 502 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 503 504 505 506 507 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 508 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 509 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 510 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 511 512 513 514 515 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 516 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 517 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 518 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 519 520 521 522 523 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 524 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 525 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 526 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff 527 528 529 530 531 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 532 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 533 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 534 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 535 536 537 538 539 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 540 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 541 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 542 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 543 544 545 546 547 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 548 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 549 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 550 #define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 551 552 553 554 555 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 556 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 557 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 558 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff 559 560 561 562 563 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 564 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 565 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 566 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 567 568 569 570 571 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 572 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 573 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 574 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 575 576 577 578 579 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 580 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 581 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 582 #define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 583 584 585 586 587 #define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 588 #define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 589 #define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 590 #define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff 591 592 593 594 595 #define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 596 #define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 597 #define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 598 #define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 599 600 601 602 603 #define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 604 #define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 605 #define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 606 #define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 607 608 609 610 611 #define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 612 #define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 613 #define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 614 #define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff 615 616 617 618 619 #define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 620 #define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 621 #define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 622 #define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 623 624 625 626 627 #define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 628 #define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 629 #define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 630 #define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff 631 632 633 634 635 #define RESPONSE_END_STATUS_RANGING_OFFSET 0x0000000000000050 636 #define RESPONSE_END_STATUS_RANGING_LSB 16 637 #define RESPONSE_END_STATUS_RANGING_MSB 16 638 #define RESPONSE_END_STATUS_RANGING_MASK 0x0000000000010000 639 640 641 642 643 #define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 644 #define RESPONSE_END_STATUS_SECURE_LSB 17 645 #define RESPONSE_END_STATUS_SECURE_MSB 17 646 #define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 647 648 649 650 651 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 652 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 653 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 654 #define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 655 656 657 658 659 #define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 660 #define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 661 #define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 662 #define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 663 664 665 666 667 #define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 668 #define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 669 #define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 670 #define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 671 672 673 674 #endif 675