1 2 /* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 27 #define _REO_UPDATE_RX_REO_QUEUE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 33 34 #define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 35 36 37 struct reo_update_rx_reo_queue { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 41 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 42 update_receive_queue_number : 1, 43 update_vld : 1, 44 update_associated_link_descriptor_counter : 1, 45 update_disable_duplicate_detection : 1, 46 update_soft_reorder_enable : 1, 47 update_ac : 1, 48 update_bar : 1, 49 update_rty : 1, 50 update_chk_2k_mode : 1, 51 update_oor_mode : 1, 52 update_ba_window_size : 1, 53 update_pn_check_needed : 1, 54 update_pn_shall_be_even : 1, 55 update_pn_shall_be_uneven : 1, 56 update_pn_handling_enable : 1, 57 update_pn_size : 1, 58 update_ignore_ampdu_flag : 1, 59 update_svld : 1, 60 update_ssn : 1, 61 update_seq_2k_error_detected_flag : 1, 62 update_pn_error_detected_flag : 1, 63 update_pn_valid : 1, 64 update_pn : 1, 65 clear_stat_counters : 1; 66 uint32_t receive_queue_number : 16, 67 vld : 1, 68 associated_link_descriptor_counter : 2, 69 disable_duplicate_detection : 1, 70 soft_reorder_enable : 1, 71 ac : 2, 72 bar : 1, 73 rty : 1, 74 chk_2k_mode : 1, 75 oor_mode : 1, 76 pn_check_needed : 1, 77 pn_shall_be_even : 1, 78 pn_shall_be_uneven : 1, 79 pn_handling_enable : 1, 80 ignore_ampdu_flag : 1; 81 uint32_t ba_window_size : 10, 82 pn_size : 2, 83 svld : 1, 84 ssn : 12, 85 seq_2k_error_detected_flag : 1, 86 pn_error_detected_flag : 1, 87 pn_valid : 1, 88 flush_from_cache : 1, 89 reserved_4a : 3; 90 uint32_t pn_31_0 : 32; 91 uint32_t pn_63_32 : 32; 92 uint32_t pn_95_64 : 32; 93 uint32_t pn_127_96 : 32; 94 uint32_t tlv64_padding : 32; 95 #else 96 struct uniform_reo_cmd_header cmd_header; 97 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 98 uint32_t clear_stat_counters : 1, 99 update_pn : 1, 100 update_pn_valid : 1, 101 update_pn_error_detected_flag : 1, 102 update_seq_2k_error_detected_flag : 1, 103 update_ssn : 1, 104 update_svld : 1, 105 update_ignore_ampdu_flag : 1, 106 update_pn_size : 1, 107 update_pn_handling_enable : 1, 108 update_pn_shall_be_uneven : 1, 109 update_pn_shall_be_even : 1, 110 update_pn_check_needed : 1, 111 update_ba_window_size : 1, 112 update_oor_mode : 1, 113 update_chk_2k_mode : 1, 114 update_rty : 1, 115 update_bar : 1, 116 update_ac : 1, 117 update_soft_reorder_enable : 1, 118 update_disable_duplicate_detection : 1, 119 update_associated_link_descriptor_counter : 1, 120 update_vld : 1, 121 update_receive_queue_number : 1, 122 rx_reo_queue_desc_addr_39_32 : 8; 123 uint32_t ignore_ampdu_flag : 1, 124 pn_handling_enable : 1, 125 pn_shall_be_uneven : 1, 126 pn_shall_be_even : 1, 127 pn_check_needed : 1, 128 oor_mode : 1, 129 chk_2k_mode : 1, 130 rty : 1, 131 bar : 1, 132 ac : 2, 133 soft_reorder_enable : 1, 134 disable_duplicate_detection : 1, 135 associated_link_descriptor_counter : 2, 136 vld : 1, 137 receive_queue_number : 16; 138 uint32_t reserved_4a : 3, 139 flush_from_cache : 1, 140 pn_valid : 1, 141 pn_error_detected_flag : 1, 142 seq_2k_error_detected_flag : 1, 143 ssn : 12, 144 svld : 1, 145 pn_size : 2, 146 ba_window_size : 10; 147 uint32_t pn_31_0 : 32; 148 uint32_t pn_63_32 : 32; 149 uint32_t pn_95_64 : 32; 150 uint32_t pn_127_96 : 32; 151 uint32_t tlv64_padding : 32; 152 #endif 153 }; 154 155 156 157 158 159 160 161 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 162 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 163 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 164 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 165 166 167 168 169 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 170 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 171 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 172 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 173 174 175 176 177 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 178 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 179 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 180 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 181 182 183 184 185 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 186 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 187 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 188 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 189 190 191 192 193 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 194 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 195 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 196 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff 197 198 199 200 201 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 202 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 203 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 204 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 205 206 207 208 209 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 210 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 211 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 212 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 213 214 215 216 217 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 218 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 219 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 220 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 221 222 223 224 225 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 226 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 227 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 228 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 229 230 231 232 233 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 234 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 235 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 236 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 237 238 239 240 241 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 242 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 243 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 244 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 245 246 247 248 249 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 250 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 251 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 252 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 253 254 255 256 257 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 258 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 259 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 260 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 261 262 263 264 265 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 266 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 267 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 268 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 269 270 271 272 273 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 274 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 275 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 276 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 277 278 279 280 281 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 282 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 283 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 284 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 285 286 287 288 289 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 290 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 291 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 292 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 293 294 295 296 297 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 298 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 299 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 300 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 301 302 303 304 305 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 306 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 307 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 308 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 309 310 311 312 313 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 314 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 315 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 316 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 317 318 319 320 321 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 322 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 323 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 324 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 325 326 327 328 329 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 330 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 331 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 332 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 333 334 335 336 337 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 338 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 339 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 340 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 341 342 343 344 345 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 346 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 347 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 348 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 349 350 351 352 353 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 354 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 355 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 356 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 357 358 359 360 361 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 362 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 363 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 364 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 365 366 367 368 369 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 370 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 371 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 372 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 373 374 375 376 377 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 378 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 379 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 380 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 381 382 383 384 385 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 386 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 387 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 388 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 389 390 391 392 393 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 394 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 395 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 396 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 397 398 399 400 401 #define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 402 #define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 403 #define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 404 #define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 405 406 407 408 409 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 410 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 411 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 412 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 413 414 415 416 417 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 418 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 419 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 420 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 421 422 423 424 425 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 426 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 427 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 428 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 429 430 431 432 433 #define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 434 #define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 435 #define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 436 #define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 437 438 439 440 441 #define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 442 #define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 443 #define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 444 #define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 445 446 447 448 449 #define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 450 #define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 451 #define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 452 #define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 453 454 455 456 457 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 458 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 459 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 460 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 461 462 463 464 465 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 466 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 467 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 468 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 469 470 471 472 473 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 474 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 475 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 476 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 477 478 479 480 481 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 482 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 483 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 484 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 485 486 487 488 489 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 490 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 491 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 492 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 493 494 495 496 497 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 498 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 499 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 500 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 501 502 503 504 505 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 506 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 507 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 508 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 509 510 511 512 513 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 514 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 515 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 516 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff 517 518 519 520 521 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 522 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 523 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 524 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 525 526 527 528 529 #define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 530 #define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 531 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 532 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 533 534 535 536 537 #define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 538 #define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 539 #define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 540 #define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 541 542 543 544 545 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 546 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 547 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 548 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 549 550 551 552 553 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 554 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 555 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 556 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 557 558 559 560 561 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 562 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 563 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 564 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 565 566 567 568 569 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 570 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 571 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 572 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 573 574 575 576 577 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 578 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 579 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 580 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 581 582 583 584 585 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 586 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 587 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 588 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 589 590 591 592 593 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 594 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 595 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 596 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff 597 598 599 600 601 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 602 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 603 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 604 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 605 606 607 608 609 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 610 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 611 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 612 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff 613 614 615 616 617 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 618 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 619 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 620 #define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 621 622 623 624 #endif 625