1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _MACTX_USER_DESC_PER_USER_H_ 27 #define _MACTX_USER_DESC_PER_USER_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 32 33 #define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 34 35 36 struct mactx_user_desc_per_user { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t psdu_length : 24, 39 reserved_0a : 8; 40 uint32_t ru_start_index : 8, 41 ru_size : 4, 42 reserved_1b : 4, 43 ofdma_mu_mimo_enabled : 1, 44 nss : 3, 45 stream_offset : 3, 46 reserved_1c : 1, 47 mcs : 4, 48 dcm : 1, 49 reserved_1d : 3; 50 uint32_t fec_type : 1, 51 reserved_2a : 7, 52 user_bf_type : 2, 53 reserved_2b : 6, 54 drop_user_cbf : 1, 55 reserved_2c : 7, 56 ldpc_extra_symbol : 1, 57 force_extra_symbol : 1, 58 reserved_2d : 6; 59 uint32_t sw_peer_id : 16, 60 per_user_subband_mask : 16; 61 #else 62 uint32_t reserved_0a : 8, 63 psdu_length : 24; 64 uint32_t reserved_1d : 3, 65 dcm : 1, 66 mcs : 4, 67 reserved_1c : 1, 68 stream_offset : 3, 69 nss : 3, 70 ofdma_mu_mimo_enabled : 1, 71 reserved_1b : 4, 72 ru_size : 4, 73 ru_start_index : 8; 74 uint32_t reserved_2d : 6, 75 force_extra_symbol : 1, 76 ldpc_extra_symbol : 1, 77 reserved_2c : 7, 78 drop_user_cbf : 1, 79 reserved_2b : 6, 80 user_bf_type : 2, 81 reserved_2a : 7, 82 fec_type : 1; 83 uint32_t per_user_subband_mask : 16, 84 sw_peer_id : 16; 85 #endif 86 }; 87 88 89 90 91 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 92 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 93 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 94 #define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff 95 96 97 98 99 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 100 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 101 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 102 #define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 103 104 105 106 107 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 108 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 109 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 110 #define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 111 112 113 114 115 #define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 116 #define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 117 #define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 118 #define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 119 120 121 122 123 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 124 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 125 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 126 #define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 127 128 129 130 131 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 132 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 133 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 134 #define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 135 136 137 138 139 #define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 140 #define MACTX_USER_DESC_PER_USER_NSS_LSB 49 141 #define MACTX_USER_DESC_PER_USER_NSS_MSB 51 142 #define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 143 144 145 146 147 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 148 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 149 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 150 #define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 151 152 153 154 155 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 156 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 157 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 158 #define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 159 160 161 162 163 #define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 164 #define MACTX_USER_DESC_PER_USER_MCS_LSB 56 165 #define MACTX_USER_DESC_PER_USER_MCS_MSB 59 166 #define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 167 168 169 170 171 #define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 172 #define MACTX_USER_DESC_PER_USER_DCM_LSB 60 173 #define MACTX_USER_DESC_PER_USER_DCM_MSB 60 174 #define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 175 176 177 178 179 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 180 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 181 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 182 #define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 183 184 185 186 187 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 188 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 189 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 190 #define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 191 192 193 194 195 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 196 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 197 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 198 #define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe 199 200 201 202 203 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 204 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 205 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 206 #define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 207 208 209 210 211 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 212 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 213 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 214 #define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 215 216 217 218 219 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 220 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 221 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 222 #define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 223 224 225 226 227 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 228 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 229 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 230 #define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 231 232 233 234 235 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 236 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 237 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 238 #define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 239 240 241 242 243 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 244 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 245 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 246 #define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 247 248 249 250 251 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 252 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 253 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 254 #define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 255 256 257 258 259 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 260 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 261 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 262 #define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 263 264 265 266 267 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 268 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 269 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 270 #define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 271 272 273 274 #endif 275