1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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25 
26 #ifndef _MACTX_U_SIG_EHT_TB_H_
27 #define _MACTX_U_SIG_EHT_TB_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "u_sig_eht_tb_info.h"
32 #define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
33 
34 #define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
35 
36 
37 struct mactx_u_sig_eht_tb {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
40 #else
41              struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
42 #endif
43 };
44 
45 
46 
47 
48 
49 
50 
51 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET       0x0000000000000000
52 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB          0
53 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB          2
54 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK         0x0000000000000007
55 
56 
57 
58 
59 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET       0x0000000000000000
60 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB          3
61 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB          5
62 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK         0x0000000000000038
63 
64 
65 
66 
67 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET        0x0000000000000000
68 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB           6
69 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB           6
70 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK          0x0000000000000040
71 
72 
73 
74 
75 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET      0x0000000000000000
76 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB         7
77 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB         12
78 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK        0x0000000000001f80
79 
80 
81 
82 
83 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET     0x0000000000000000
84 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB        13
85 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB        19
86 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK       0x00000000000fe000
87 
88 
89 
90 
91 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET      0x0000000000000000
92 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB         20
93 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB         25
94 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK        0x0000000003f00000
95 
96 
97 
98 
99 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET       0x0000000000000000
100 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB          26
101 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB          31
102 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK         0x00000000fc000000
103 
104 
105 
106 
107 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
108 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
109 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
110 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
111 
112 
113 
114 
115 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET       0x0000000000000000
116 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB          34
117 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB          34
118 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK         0x0000000400000000
119 
120 
121 
122 
123 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET     0x0000000000000000
124 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB        35
125 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB        42
126 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK       0x000007f800000000
127 
128 
129 
130 
131 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET      0x0000000000000000
132 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB         43
133 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB         47
134 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK        0x0000f80000000000
135 
136 
137 
138 
139 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET               0x0000000000000000
140 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB                  48
141 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB                  51
142 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK                 0x000f000000000000
143 
144 
145 
146 
147 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET              0x0000000000000000
148 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB                 52
149 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB                 57
150 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK                0x03f0000000000000
151 
152 
153 
154 
155 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET       0x0000000000000000
156 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB          58
157 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB          62
158 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK         0x7c00000000000000
159 
160 
161 
162 
163 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
164 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
165 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
166 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
167 
168 
169 
170 #endif
171