1 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 19 20 21 22 23 24 25 26 27 #ifndef _HE_SIG_A_MU_UL_INFO_H_ 28 #define _HE_SIG_A_MU_UL_INFO_H_ 29 #if !defined(__ASSEMBLER__) 30 #endif 31 32 #define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 33 34 35 struct he_sig_a_mu_ul_info { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 uint32_t format_indication : 1, // [0:0] 38 bss_color_id : 6, // [6:1] 39 spatial_reuse : 16, // [22:7] 40 reserved_0a : 1, // [23:23] 41 transmit_bw : 2, // [25:24] 42 reserved_0b : 6; // [31:26] 43 uint32_t txop_duration : 7, // [6:0] 44 reserved_1a : 9, // [15:7] 45 crc : 4, // [19:16] 46 tail : 6, // [25:20] 47 reserved_1b : 5, // [30:26] 48 rx_integrity_check_passed : 1; // [31:31] 49 #else 50 uint32_t reserved_0b : 6, // [31:26] 51 transmit_bw : 2, // [25:24] 52 reserved_0a : 1, // [23:23] 53 spatial_reuse : 16, // [22:7] 54 bss_color_id : 6, // [6:1] 55 format_indication : 1; // [0:0] 56 uint32_t rx_integrity_check_passed : 1, // [31:31] 57 reserved_1b : 5, // [30:26] 58 tail : 6, // [25:20] 59 crc : 4, // [19:16] 60 reserved_1a : 9, // [15:7] 61 txop_duration : 7; // [6:0] 62 #endif 63 }; 64 65 66 67 68 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 69 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 70 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 71 #define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 72 73 74 75 76 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 77 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 78 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 79 #define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e 80 81 82 83 84 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 85 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 86 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 87 #define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 88 89 90 91 92 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 93 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 94 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 95 #define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 96 97 98 99 100 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 101 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 102 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 103 #define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 104 105 106 107 108 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 109 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 110 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 111 #define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 112 113 114 115 116 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 117 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 118 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 119 #define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f 120 121 122 123 124 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 125 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 126 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 127 #define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 128 129 130 131 132 #define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 133 #define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 134 #define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 135 #define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 136 137 138 139 140 #define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 141 #define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 142 #define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 143 #define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 144 145 146 147 148 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 149 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 150 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 151 #define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 152 153 154 155 156 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 157 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 158 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 159 #define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 160 161 162 163 164 #endif 165