1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _EXPECTED_RESPONSE_H_ 27 #define _EXPECTED_RESPONSE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 32 33 #define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 34 35 36 struct expected_response { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t tx_ad2_31_0 : 32; 39 uint32_t tx_ad2_47_32 : 16, 40 expected_response_type : 5, 41 response_to_response : 3, 42 su_ba_user_number : 1, 43 response_info_part2_required : 1, 44 transmitted_bssid_check_en : 1, 45 reserved_1 : 5; 46 uint32_t ndp_sta_partial_aid_2_8_0 : 11, 47 reserved_2 : 10, 48 ndp_sta_partial_aid1_8_0 : 11; 49 uint32_t ast_index : 16, 50 capture_ack_ba_sounding : 1, 51 capture_sounding_1str_20mhz : 1, 52 capture_sounding_1str_40mhz : 1, 53 capture_sounding_1str_80mhz : 1, 54 capture_sounding_1str_160mhz : 1, 55 capture_sounding_1str_240mhz : 1, 56 capture_sounding_1str_320mhz : 1, 57 reserved_3a : 9; 58 uint32_t fcs : 9, 59 reserved_4a : 1, 60 crc : 4, 61 scrambler_seed : 7, 62 reserved_4b : 11; 63 uint32_t tlv64_padding : 32; 64 #else 65 uint32_t tx_ad2_31_0 : 32; 66 uint32_t reserved_1 : 5, 67 transmitted_bssid_check_en : 1, 68 response_info_part2_required : 1, 69 su_ba_user_number : 1, 70 response_to_response : 3, 71 expected_response_type : 5, 72 tx_ad2_47_32 : 16; 73 uint32_t ndp_sta_partial_aid1_8_0 : 11, 74 reserved_2 : 10, 75 ndp_sta_partial_aid_2_8_0 : 11; 76 uint32_t reserved_3a : 9, 77 capture_sounding_1str_320mhz : 1, 78 capture_sounding_1str_240mhz : 1, 79 capture_sounding_1str_160mhz : 1, 80 capture_sounding_1str_80mhz : 1, 81 capture_sounding_1str_40mhz : 1, 82 capture_sounding_1str_20mhz : 1, 83 capture_ack_ba_sounding : 1, 84 ast_index : 16; 85 uint32_t reserved_4b : 11, 86 scrambler_seed : 7, 87 crc : 4, 88 reserved_4a : 1, 89 fcs : 9; 90 uint32_t tlv64_padding : 32; 91 #endif 92 }; 93 94 95 96 97 #define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 98 #define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 99 #define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 100 #define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff 101 102 103 104 105 #define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 106 #define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 107 #define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 108 #define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 109 110 111 112 113 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 114 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 115 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 116 #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 117 118 119 120 121 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 122 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 123 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 124 #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 125 126 127 128 129 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 130 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 131 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 132 #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 133 134 135 136 137 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 138 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 139 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 140 #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 141 142 143 144 145 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 146 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 147 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 148 #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 149 150 151 152 153 #define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 154 #define EXPECTED_RESPONSE_RESERVED_1_LSB 59 155 #define EXPECTED_RESPONSE_RESERVED_1_MSB 63 156 #define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 157 158 159 160 161 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 162 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 163 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 164 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff 165 166 167 168 169 #define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 170 #define EXPECTED_RESPONSE_RESERVED_2_LSB 11 171 #define EXPECTED_RESPONSE_RESERVED_2_MSB 20 172 #define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 173 174 175 176 177 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 178 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 179 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 180 #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 181 182 183 184 185 #define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 186 #define EXPECTED_RESPONSE_AST_INDEX_LSB 32 187 #define EXPECTED_RESPONSE_AST_INDEX_MSB 47 188 #define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 189 190 191 192 193 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 194 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 195 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 196 #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 197 198 199 200 201 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 202 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 203 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 204 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 205 206 207 208 209 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 210 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 211 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 212 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 213 214 215 216 217 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 218 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 219 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 220 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 221 222 223 224 225 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 226 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 227 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 228 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 229 230 231 232 233 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 234 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 235 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 236 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 237 238 239 240 241 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 242 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 243 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 244 #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 245 246 247 248 249 #define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 250 #define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 251 #define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 252 #define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 253 254 255 256 257 #define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 258 #define EXPECTED_RESPONSE_FCS_LSB 0 259 #define EXPECTED_RESPONSE_FCS_MSB 8 260 #define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff 261 262 263 264 265 #define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 266 #define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 267 #define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 268 #define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 269 270 271 272 273 #define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 274 #define EXPECTED_RESPONSE_CRC_LSB 10 275 #define EXPECTED_RESPONSE_CRC_MSB 13 276 #define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 277 278 279 280 281 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 282 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 283 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 284 #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 285 286 287 288 289 #define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 290 #define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 291 #define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 292 #define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 293 294 295 296 297 #define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 298 #define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 299 #define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 300 #define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 301 302 303 304 #endif 305