1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _TCL_GSE_CMD_H_ 24 #define _TCL_GSE_CMD_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 29 // ################ START SUMMARY ################# 30 // 31 // Dword Fields 32 // 0 control_buffer_addr_31_0[31:0] 33 // 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20] 34 // 2 cmd_meta_data_31_0[31:0] 35 // 3 cmd_meta_data_63_32[31:0] 36 // 4 reserved_4a[31:0] 37 // 5 reserved_5a[31:0] 38 // 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] 39 // 40 // ################ END SUMMARY ################# 41 42 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 43 44 struct tcl_gse_cmd { 45 uint32_t control_buffer_addr_31_0 : 32; //[31:0] 46 uint32_t control_buffer_addr_39_32 : 8, //[7:0] 47 gse_ctrl : 4, //[11:8] 48 gse_sel : 1, //[12] 49 status_destination_ring_id : 1, //[13] 50 swap : 1, //[14] 51 index_search_en : 1, //[15] 52 cache_set_num : 4, //[19:16] 53 reserved_1a : 12; //[31:20] 54 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 55 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 56 uint32_t reserved_4a : 32; //[31:0] 57 uint32_t reserved_5a : 32; //[31:0] 58 uint32_t reserved_6a : 20, //[19:0] 59 ring_id : 8, //[27:20] 60 looping_count : 4; //[31:28] 61 }; 62 63 /* 64 65 control_buffer_addr_31_0 66 67 Address (lower 32 bits) of a control buffer containing 68 additional info needed for this command execution. 69 70 <legal all> 71 72 control_buffer_addr_39_32 73 74 Address (upper 8 bits) of a control buffer containing 75 additional info needed for this command execution. 76 77 <legal all> 78 79 gse_ctrl 80 81 GSE control operations. This includes cache operations 82 and table entry statistics read/clear operation. 83 84 <enum 0 rd_stat> Report or Read statistics 85 86 <enum 1 srch_dis> Search disable. Report only Hash 87 88 <enum 2 Wr_bk_single> Write Back single entry 89 90 <enum 3 wr_bk_all> Write Back entire cache entry 91 92 <enum 4 inval_single> Invalidate single cache entry 93 94 <enum 5 inval_all> Invalidate entire cache 95 96 <enum 6 wr_bk_inval_single> Write back and Invalidate 97 single entry in cache 98 99 <enum 7 wr_bk_inval_all> write back and invalidate 100 entire cache 101 102 <enum 8 clr_stat_single> Clear statistics for single 103 entry 104 105 <legal 0-8> 106 107 Rest of the values reserved. 108 109 For all single entry control operations (write back, 110 Invalidate or both)Statistics will be reported 111 112 gse_sel 113 114 Bit to select the ASE or FSE to do the operation mention 115 by GSE_ctrl bit 116 117 0: FSE select 118 119 1: ASE select 120 121 status_destination_ring_id 122 123 The TCL status ring to which the GSE status needs to be 124 send. 125 126 127 128 <enum 0 tcl_status_0_ring> 129 130 <enum 1 tcl_status_1_ring> 131 132 133 134 <legal all> 135 136 swap 137 138 Bit to enable byte swapping of contents of buffer 139 140 <enum 0 Byte_swap_disable > 141 142 <enum 1 byte_swap_enable > 143 144 <legal all> 145 146 index_search_en 147 148 When this bit is set to 1 control_buffer_addr[19:0] will 149 be considered as index of the AST or Flow table and GSE 150 commands will be executed accordingly on the entry pointed 151 by the index. 152 153 This feature is disabled by setting this bit to 0. 154 155 <enum 0 index_based_cmd_disable> 156 157 <enum 1 index_based_cmd_enable> 158 159 160 161 <legal all> 162 163 cache_set_num 164 165 Cache set number that should be used to cache the index 166 based search results, for address and flow search. This 167 value should be equal to value of cache_set_num for the 168 index that is issued in TCL_DATA_CMD during search index 169 based ASE or FSE. This field is valid for index based GSE 170 commands 171 172 <legal all> 173 174 reserved_1a 175 176 <legal 0> 177 178 cmd_meta_data_31_0 179 180 Meta data to be returned in the status descriptor 181 182 <legal all> 183 184 cmd_meta_data_63_32 185 186 Meta data to be returned in the status descriptor 187 188 <legal all> 189 190 reserved_4a 191 192 <legal 0> 193 194 reserved_5a 195 196 <legal 0> 197 198 reserved_6a 199 200 <legal 0> 201 202 ring_id 203 204 Helps with debugging when dumping ring contents. 205 206 <legal all> 207 208 looping_count 209 210 A count value that indicates the number of times the 211 producer of entries into the Ring has looped around the 212 ring. 213 214 At initialization time, this value is set to 0. On the 215 first loop, this value is set to 1. After the max value is 216 reached allowed by the number of bits for this field, the 217 count value continues with 0 again. 218 219 220 221 In case SW is the consumer of the ring entries, it can 222 use this field to figure out up to where the producer of 223 entries has created new entries. This eliminates the need to 224 check where the head pointer' of the ring is located once 225 the SW starts processing an interrupt indicating that new 226 entries have been put into this ring... 227 228 229 230 Also note that SW if it wants only needs to look at the 231 LSB bit of this count value. 232 233 <legal all> 234 */ 235 236 237 /* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 238 239 Address (lower 32 bits) of a control buffer containing 240 additional info needed for this command execution. 241 242 <legal all> 243 */ 244 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 245 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 246 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 247 248 /* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 249 250 Address (upper 8 bits) of a control buffer containing 251 additional info needed for this command execution. 252 253 <legal all> 254 */ 255 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 256 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 257 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 258 259 /* Description TCL_GSE_CMD_1_GSE_CTRL 260 261 GSE control operations. This includes cache operations 262 and table entry statistics read/clear operation. 263 264 <enum 0 rd_stat> Report or Read statistics 265 266 <enum 1 srch_dis> Search disable. Report only Hash 267 268 <enum 2 Wr_bk_single> Write Back single entry 269 270 <enum 3 wr_bk_all> Write Back entire cache entry 271 272 <enum 4 inval_single> Invalidate single cache entry 273 274 <enum 5 inval_all> Invalidate entire cache 275 276 <enum 6 wr_bk_inval_single> Write back and Invalidate 277 single entry in cache 278 279 <enum 7 wr_bk_inval_all> write back and invalidate 280 entire cache 281 282 <enum 8 clr_stat_single> Clear statistics for single 283 entry 284 285 <legal 0-8> 286 287 Rest of the values reserved. 288 289 For all single entry control operations (write back, 290 Invalidate or both)Statistics will be reported 291 */ 292 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 293 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 294 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 295 296 /* Description TCL_GSE_CMD_1_GSE_SEL 297 298 Bit to select the ASE or FSE to do the operation mention 299 by GSE_ctrl bit 300 301 0: FSE select 302 303 1: ASE select 304 */ 305 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 306 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 307 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 308 309 /* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID 310 311 The TCL status ring to which the GSE status needs to be 312 send. 313 314 315 316 <enum 0 tcl_status_0_ring> 317 318 <enum 1 tcl_status_1_ring> 319 320 321 322 <legal all> 323 */ 324 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 325 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 326 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 327 328 /* Description TCL_GSE_CMD_1_SWAP 329 330 Bit to enable byte swapping of contents of buffer 331 332 <enum 0 Byte_swap_disable > 333 334 <enum 1 byte_swap_enable > 335 336 <legal all> 337 */ 338 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 339 #define TCL_GSE_CMD_1_SWAP_LSB 14 340 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 341 342 /* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN 343 344 When this bit is set to 1 control_buffer_addr[19:0] will 345 be considered as index of the AST or Flow table and GSE 346 commands will be executed accordingly on the entry pointed 347 by the index. 348 349 This feature is disabled by setting this bit to 0. 350 351 <enum 0 index_based_cmd_disable> 352 353 <enum 1 index_based_cmd_enable> 354 355 356 357 <legal all> 358 */ 359 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 360 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 361 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 362 363 /* Description TCL_GSE_CMD_1_CACHE_SET_NUM 364 365 Cache set number that should be used to cache the index 366 based search results, for address and flow search. This 367 value should be equal to value of cache_set_num for the 368 index that is issued in TCL_DATA_CMD during search index 369 based ASE or FSE. This field is valid for index based GSE 370 commands 371 372 <legal all> 373 */ 374 #define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 375 #define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 376 #define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 377 378 /* Description TCL_GSE_CMD_1_RESERVED_1A 379 380 <legal 0> 381 */ 382 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 383 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 384 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 385 386 /* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 387 388 Meta data to be returned in the status descriptor 389 390 <legal all> 391 */ 392 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 393 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 394 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 395 396 /* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 397 398 Meta data to be returned in the status descriptor 399 400 <legal all> 401 */ 402 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 403 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 404 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 405 406 /* Description TCL_GSE_CMD_4_RESERVED_4A 407 408 <legal 0> 409 */ 410 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 411 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 412 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 413 414 /* Description TCL_GSE_CMD_5_RESERVED_5A 415 416 <legal 0> 417 */ 418 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 419 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 420 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 421 422 /* Description TCL_GSE_CMD_6_RESERVED_6A 423 424 <legal 0> 425 */ 426 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 427 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 428 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 429 430 /* Description TCL_GSE_CMD_6_RING_ID 431 432 Helps with debugging when dumping ring contents. 433 434 <legal all> 435 */ 436 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 437 #define TCL_GSE_CMD_6_RING_ID_LSB 20 438 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 439 440 /* Description TCL_GSE_CMD_6_LOOPING_COUNT 441 442 A count value that indicates the number of times the 443 producer of entries into the Ring has looped around the 444 ring. 445 446 At initialization time, this value is set to 0. On the 447 first loop, this value is set to 1. After the max value is 448 reached allowed by the number of bits for this field, the 449 count value continues with 0 again. 450 451 452 453 In case SW is the consumer of the ring entries, it can 454 use this field to figure out up to where the producer of 455 entries has created new entries. This eliminates the need to 456 check where the head pointer' of the ring is located once 457 the SW starts processing an interrupt indicating that new 458 entries have been put into this ring... 459 460 461 462 Also note that SW if it wants only needs to look at the 463 LSB bit of this count value. 464 465 <legal all> 466 */ 467 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 468 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 469 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 470 471 472 #endif // _TCL_GSE_CMD_H_ 473