1 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16 // $ATH_LICENSE_HW_HDR_C$ 17 // 18 // DO NOT EDIT! This file is automatically generated 19 // These definitions are tied to a particular hardware layout 20 21 22 #ifndef _REO_ENTRANCE_RING_H_ 23 #define _REO_ENTRANCE_RING_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rx_mpdu_details.h" 28 29 // ################ START SUMMARY ################# 30 // 31 // Dword Fields 32 // 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; 33 // 4 rx_reo_queue_desc_addr_31_0[31:0] 34 // 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] 35 // 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], reserved_6a[31:11] 36 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 37 // 38 // ################ END SUMMARY ################# 39 40 #define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 41 42 struct reo_entrance_ring { 43 struct rx_mpdu_details reo_level_mpdu_frame_info; 44 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 45 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 46 rounded_mpdu_byte_count : 14, //[21:8] 47 reo_destination_indication : 5, //[26:22] 48 frameless_bar : 1, //[27] 49 reserved_5a : 4; //[31:28] 50 uint32_t rxdma_push_reason : 2, //[1:0] 51 rxdma_error_code : 5, //[6:2] 52 mpdu_fragment_number : 4, //[10:7] 53 reserved_6a : 21; //[31:11] 54 uint32_t reserved_7a : 20, //[19:0] 55 ring_id : 8, //[27:20] 56 looping_count : 4; //[31:28] 57 }; 58 59 /* 60 61 struct rx_mpdu_details reo_level_mpdu_frame_info 62 63 Consumer: REO 64 65 Producer: RXDMA 66 67 68 69 Details related to the MPDU being pushed into the REO 70 71 rx_reo_queue_desc_addr_31_0 72 73 Consumer: REO 74 75 Producer: RXDMA 76 77 78 79 Address (lower 32 bits) of the REO queue descriptor. 80 81 <legal all> 82 83 rx_reo_queue_desc_addr_39_32 84 85 Consumer: REO 86 87 Producer: RXDMA 88 89 90 91 Address (upper 8 bits) of the REO queue descriptor. 92 93 <legal all> 94 95 rounded_mpdu_byte_count 96 97 An approximation of the number of bytes received in this 98 MPDU. 99 100 Used to keeps stats on the amount of data flowing 101 through a queue. 102 103 <legal all> 104 105 reo_destination_indication 106 107 RXDMA copy the MPDU's first MSDU's destination 108 indication field here. This is used for REO to be able to 109 re-route the packet to a different SW destination ring if 110 the packet is detected as error in REO. 111 112 113 114 The ID of the REO exit ring where the MSDU frame shall 115 push after (MPDU level) reordering has finished. 116 117 118 119 <enum 0 reo_destination_tcl> Reo will push the frame 120 into the REO2TCL ring 121 122 <enum 1 reo_destination_sw1> Reo will push the frame 123 into the REO2SW1 ring 124 125 <enum 2 reo_destination_sw2> Reo will push the frame 126 into the REO2SW1 ring 127 128 <enum 3 reo_destination_sw3> Reo will push the frame 129 into the REO2SW1 ring 130 131 <enum 4 reo_destination_sw4> Reo will push the frame 132 into the REO2SW1 ring 133 134 <enum 5 reo_destination_release> Reo will push the frame 135 into the REO_release ring 136 137 <enum 6 reo_destination_fw> Reo will push the frame into 138 the REO2FW ring 139 140 <enum 7 reo_destination_7> REO remaps this 141 142 <enum 8 reo_destination_8> REO remaps this <enum 9 143 reo_destination_9> REO remaps this <enum 10 144 reo_destination_10> REO remaps this 145 146 <enum 11 reo_destination_11> REO remaps this 147 148 <enum 12 reo_destination_12> REO remaps this <enum 13 149 reo_destination_13> REO remaps this 150 151 <enum 14 reo_destination_14> REO remaps this 152 153 <enum 15 reo_destination_15> REO remaps this 154 155 <enum 16 reo_destination_16> REO remaps this 156 157 <enum 17 reo_destination_17> REO remaps this 158 159 <enum 18 reo_destination_18> REO remaps this 160 161 <enum 19 reo_destination_19> REO remaps this 162 163 <enum 20 reo_destination_20> REO remaps this 164 165 <enum 21 reo_destination_21> REO remaps this 166 167 <enum 22 reo_destination_22> REO remaps this 168 169 <enum 23 reo_destination_23> REO remaps this 170 171 <enum 24 reo_destination_24> REO remaps this 172 173 <enum 25 reo_destination_25> REO remaps this 174 175 <enum 26 reo_destination_26> REO remaps this 176 177 <enum 27 reo_destination_27> REO remaps this 178 179 <enum 28 reo_destination_28> REO remaps this 180 181 <enum 29 reo_destination_29> REO remaps this 182 183 <enum 30 reo_destination_30> REO remaps this 184 185 <enum 31 reo_destination_31> REO remaps this 186 187 188 189 <legal all> 190 191 frameless_bar 192 193 When set, this REO entrance ring struct contains BAR 194 info from a multi TID BAR frame. The original multi TID BAR 195 frame itself contained all the REO info for the first TID, 196 but all the subsequent TID info and their linkage to the REO 197 descriptors is passed down as 'frameless' BAR info. 198 199 200 201 The only fields valid in this descriptor when this bit 202 is set are: 203 204 Rx_reo_queue_desc_addr_31_0 205 206 RX_reo_queue_desc_addr_39_32 207 208 209 210 And within the 211 212 Reo_level_mpdu_frame_info: 213 214 Within Rx_mpdu_desc_info_details: 215 216 Mpdu_Sequence_number 217 218 BAR_frame 219 220 Peer_meta_data 221 222 All other fields shall be set to 0 223 224 225 226 <legal all> 227 228 reserved_5a 229 230 <legal 0> 231 232 rxdma_push_reason 233 234 Indicates why rxdma pushed the frame to this ring 235 236 237 238 This field is ignored by REO. 239 240 241 242 <enum 0 rxdma_error_detected> RXDMA detected an error an 243 pushed this frame to this queue 244 245 <enum 1 rxdma_routing_instruction> RXDMA pushed the 246 frame to this queue per received routing instructions. No 247 error within RXDMA was detected 248 249 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 250 result the MSDU link descriptor might not have the 251 last_msdu_in_mpdu_flag set, but instead WBM might just see a 252 NULL pointer in the MSDU link descriptor. This is to be 253 considered a normal condition for this scenario. 254 255 256 257 <legal 0 - 2> 258 259 rxdma_error_code 260 261 Field only valid when 'rxdma_push_reason' set to 262 'rxdma_error_detected'. 263 264 265 266 This field is ignored by REO. 267 268 269 270 <enum 0 rxdma_overflow_err>MPDU frame is not complete 271 due to a FIFO overflow error in RXPCU. 272 273 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 274 due to receiving incomplete MPDU from the PHY 275 276 277 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 278 error or CRYPTO received an encrypted frame, but did not get 279 a valid corresponding key id in the peer entry. 280 281 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 282 error 283 284 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 285 unencrypted frame error when encrypted was expected 286 287 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 288 length error 289 290 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 291 number of MSDUs allowed in an MPDU got exceeded 292 293 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 294 error 295 296 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 297 parsing error 298 299 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 300 during SA search 301 302 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 303 during DA search 304 305 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 306 timeout during flow search 307 308 <enum 13 Rxdma_flush_request>RXDMA received a flush 309 request 310 311 mpdu_fragment_number 312 313 Field only valid when Reo_level_mpdu_frame_info. 314 315 Rx_mpdu_desc_info_details. 316 317 Fragment_flag is set. 318 319 320 321 The fragment number from the 802.11 header. 322 323 324 325 Note that the sequence number is embedded in field: 326 Reo_level_mpdu_frame_info. 327 328 Rx_mpdu_desc_info_details. 329 330 Mpdu_Sequence_number 331 332 333 334 <legal all> 335 336 reserved_6a 337 338 <legal 0> 339 340 reserved_7a 341 342 <legal 0> 343 344 ring_id 345 346 Consumer: SW/REO/DEBUG 347 348 Producer: SRNG (of RXDMA) 349 350 351 352 For debugging. 353 354 This field is filled in by the SRNG module. 355 356 It help to identify the ring that is being looked <legal 357 all> 358 359 looping_count 360 361 Consumer: SW/REO/DEBUG 362 363 Producer: SRNG (of RXDMA) 364 365 366 367 For debugging. 368 369 This field is filled in by the SRNG module. 370 371 372 373 A count value that indicates the number of times the 374 producer of entries into this Ring has looped around the 375 ring. 376 377 At initialization time, this value is set to 0. On the 378 first loop, this value is set to 1. After the max value is 379 reached allowed by the number of bits for this field, the 380 count value continues with 0 again. 381 382 383 384 In case SW is the consumer of the ring entries, it can 385 use this field to figure out up to where the producer of 386 entries has created new entries. This eliminates the need to 387 check where the head pointer' of the ring is located once 388 the SW starts processing an interrupt indicating that new 389 entries have been put into this ring... 390 391 392 393 Also note that SW if it wants only needs to look at the 394 LSB bit of this count value. 395 396 <legal all> 397 */ 398 399 400 /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ 401 402 403 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 404 405 406 /* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 407 408 Address (lower 32 bits) of the MSDU buffer OR 409 MSDU_EXTENSION descriptor OR Link Descriptor 410 411 412 413 In case of 'NULL' pointer, this field is set to 0 414 415 <legal all> 416 */ 417 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 418 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 419 #define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 420 421 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 422 423 Address (upper 8 bits) of the MSDU buffer OR 424 MSDU_EXTENSION descriptor OR Link Descriptor 425 426 427 428 In case of 'NULL' pointer, this field is set to 0 429 430 <legal all> 431 */ 432 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 433 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 434 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 435 436 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 437 438 Consumer: WBM 439 440 Producer: SW/FW 441 442 443 444 In case of 'NULL' pointer, this field is set to 0 445 446 447 448 Indicates to which buffer manager the buffer OR 449 MSDU_EXTENSION descriptor OR link descriptor that is being 450 pointed to shall be returned after the frame has been 451 processed. It is used by WBM for routing purposes. 452 453 454 455 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 456 to the WMB buffer idle list 457 458 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 459 returned to the WMB idle link descriptor idle list 460 461 <enum 2 FW_BM> This buffer shall be returned to the FW 462 463 <enum 3 SW0_BM> This buffer shall be returned to the SW, 464 ring 0 465 466 <enum 4 SW1_BM> This buffer shall be returned to the SW, 467 ring 1 468 469 <enum 5 SW2_BM> This buffer shall be returned to the SW, 470 ring 2 471 472 <enum 6 SW3_BM> This buffer shall be returned to the SW, 473 ring 3 474 475 <enum 7 SW4_BM> This buffer shall be returned to the SW, 476 ring 3 477 478 479 480 <legal all> 481 */ 482 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 483 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 484 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 485 486 /* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 487 488 Cookie field exclusively used by SW. 489 490 491 492 In case of 'NULL' pointer, this field is set to 0 493 494 495 496 HW ignores the contents, accept that it passes the 497 programmed value on to other descriptors together with the 498 physical address 499 500 501 502 Field can be used by SW to for example associate the 503 buffers physical address with the virtual address 504 505 The bit definitions as used by SW are within SW HLD 506 specification 507 508 509 510 NOTE: 511 512 The three most significant bits can have a special 513 meaning in case this struct is embedded in a TX_MPDU_DETAILS 514 STRUCT, and field transmit_bw_restriction is set 515 516 517 518 In case of NON punctured transmission: 519 520 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 521 522 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 523 524 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 525 526 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 527 528 529 530 In case of punctured transmission: 531 532 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 533 534 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 535 536 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 537 538 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 539 540 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 541 542 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 543 544 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 545 546 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 547 548 549 550 Note: a punctured transmission is indicated by the 551 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 552 TLV 553 554 555 556 <legal all> 557 */ 558 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 559 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 560 #define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 561 562 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 563 564 565 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 566 567 Consumer: REO/SW/FW 568 569 Producer: RXDMA 570 571 572 573 The number of MSDUs within the MPDU 574 575 <legal all> 576 */ 577 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 578 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 579 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 580 581 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 582 583 Consumer: REO/SW/FW 584 585 Producer: RXDMA 586 587 588 589 The field can have two different meanings based on the 590 setting of field 'BAR_frame': 591 592 593 594 'BAR_frame' is NOT set: 595 596 The MPDU sequence number of the received frame. 597 598 599 600 'BAR_frame' is set. 601 602 The MPDU Start sequence number from the BAR frame 603 604 <legal all> 605 */ 606 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 607 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 608 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 609 610 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 611 612 Consumer: REO/SW/FW 613 614 Producer: RXDMA 615 616 617 618 When set, this MPDU is a fragment and REO should forward 619 this fragment MPDU to the REO destination ring without any 620 reorder checks, pn checks or bitmap update. This implies 621 that REO is forwarding the pointer to the MSDU link 622 descriptor. The destination ring is coming from a 623 programmable register setting in REO 624 625 626 627 <legal all> 628 */ 629 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 630 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 631 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 632 633 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 634 635 Consumer: REO/SW/FW 636 637 Producer: RXDMA 638 639 640 641 The retry bit setting from the MPDU header of the 642 received frame 643 644 <legal all> 645 */ 646 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 647 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 648 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 649 650 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 651 652 Consumer: REO/SW/FW 653 654 Producer: RXDMA 655 656 657 658 When set, the MPDU was received as part of an A-MPDU. 659 660 <legal all> 661 */ 662 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 663 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 664 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 665 666 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 667 668 Consumer: REO/SW/FW 669 670 Producer: RXDMA 671 672 673 674 When set, the received frame is a BAR frame. After 675 processing, this frame shall be pushed to SW or deleted. 676 677 <legal all> 678 */ 679 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 680 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 681 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 682 683 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 684 685 Consumer: REO/SW/FW 686 687 Producer: RXDMA 688 689 690 691 Copied here by RXDMA from RX_MPDU_END 692 693 When not set, REO will Not perform a PN sequence number 694 check 695 */ 696 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 697 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 698 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 699 700 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 701 702 When set, OLE found a valid SA entry for all MSDUs in 703 this MPDU 704 705 <legal all> 706 */ 707 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 708 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 709 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 710 711 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 712 713 When set, at least 1 MSDU within the MPDU has an 714 unsuccessful MAC source address search due to the expiration 715 of the search timer. 716 717 <legal all> 718 */ 719 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 720 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 721 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 722 723 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 724 725 When set, OLE found a valid DA entry for all MSDUs in 726 this MPDU 727 728 <legal all> 729 */ 730 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 731 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 732 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 733 734 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 735 736 Field Only valid if da_is_valid is set 737 738 739 740 When set, at least one of the DA addresses is a 741 Multicast or Broadcast address. 742 743 <legal all> 744 */ 745 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 746 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 747 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 748 749 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 750 751 When set, at least 1 MSDU within the MPDU has an 752 unsuccessful MAC destination address search due to the 753 expiration of the search timer. 754 755 <legal all> 756 */ 757 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 758 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 759 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 760 761 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 762 763 Field only valid when first_msdu_in_mpdu_flag is set. 764 765 766 767 When set, the contents in the MSDU buffer contains a 768 'RAW' MPDU. This 'RAW' MPDU might be spread out over 769 multiple MSDU buffers. 770 771 <legal all> 772 */ 773 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 774 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 775 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 776 777 /* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 778 779 The More Fragment bit setting from the MPDU header of 780 the received frame 781 782 783 784 <legal all> 785 */ 786 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 787 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 788 #define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 789 790 /* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 791 792 Meta data that SW has programmed in the Peer table entry 793 of the transmitting STA. 794 795 <legal all> 796 */ 797 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 798 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 799 #define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 800 801 /* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 802 803 Consumer: REO 804 805 Producer: RXDMA 806 807 808 809 Address (lower 32 bits) of the REO queue descriptor. 810 811 <legal all> 812 */ 813 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 814 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 815 #define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 816 817 /* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 818 819 Consumer: REO 820 821 Producer: RXDMA 822 823 824 825 Address (upper 8 bits) of the REO queue descriptor. 826 827 <legal all> 828 */ 829 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 830 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 831 #define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 832 833 /* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT 834 835 An approximation of the number of bytes received in this 836 MPDU. 837 838 Used to keeps stats on the amount of data flowing 839 through a queue. 840 841 <legal all> 842 */ 843 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 844 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 845 #define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 846 847 /* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION 848 849 RXDMA copy the MPDU's first MSDU's destination 850 indication field here. This is used for REO to be able to 851 re-route the packet to a different SW destination ring if 852 the packet is detected as error in REO. 853 854 855 856 The ID of the REO exit ring where the MSDU frame shall 857 push after (MPDU level) reordering has finished. 858 859 860 861 <enum 0 reo_destination_tcl> Reo will push the frame 862 into the REO2TCL ring 863 864 <enum 1 reo_destination_sw1> Reo will push the frame 865 into the REO2SW1 ring 866 867 <enum 2 reo_destination_sw2> Reo will push the frame 868 into the REO2SW1 ring 869 870 <enum 3 reo_destination_sw3> Reo will push the frame 871 into the REO2SW1 ring 872 873 <enum 4 reo_destination_sw4> Reo will push the frame 874 into the REO2SW1 ring 875 876 <enum 5 reo_destination_release> Reo will push the frame 877 into the REO_release ring 878 879 <enum 6 reo_destination_fw> Reo will push the frame into 880 the REO2FW ring 881 882 <enum 7 reo_destination_7> REO remaps this 883 884 <enum 8 reo_destination_8> REO remaps this <enum 9 885 reo_destination_9> REO remaps this <enum 10 886 reo_destination_10> REO remaps this 887 888 <enum 11 reo_destination_11> REO remaps this 889 890 <enum 12 reo_destination_12> REO remaps this <enum 13 891 reo_destination_13> REO remaps this 892 893 <enum 14 reo_destination_14> REO remaps this 894 895 <enum 15 reo_destination_15> REO remaps this 896 897 <enum 16 reo_destination_16> REO remaps this 898 899 <enum 17 reo_destination_17> REO remaps this 900 901 <enum 18 reo_destination_18> REO remaps this 902 903 <enum 19 reo_destination_19> REO remaps this 904 905 <enum 20 reo_destination_20> REO remaps this 906 907 <enum 21 reo_destination_21> REO remaps this 908 909 <enum 22 reo_destination_22> REO remaps this 910 911 <enum 23 reo_destination_23> REO remaps this 912 913 <enum 24 reo_destination_24> REO remaps this 914 915 <enum 25 reo_destination_25> REO remaps this 916 917 <enum 26 reo_destination_26> REO remaps this 918 919 <enum 27 reo_destination_27> REO remaps this 920 921 <enum 28 reo_destination_28> REO remaps this 922 923 <enum 29 reo_destination_29> REO remaps this 924 925 <enum 30 reo_destination_30> REO remaps this 926 927 <enum 31 reo_destination_31> REO remaps this 928 929 930 931 <legal all> 932 */ 933 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 934 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 935 #define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 936 937 /* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR 938 939 When set, this REO entrance ring struct contains BAR 940 info from a multi TID BAR frame. The original multi TID BAR 941 frame itself contained all the REO info for the first TID, 942 but all the subsequent TID info and their linkage to the REO 943 descriptors is passed down as 'frameless' BAR info. 944 945 946 947 The only fields valid in this descriptor when this bit 948 is set are: 949 950 Rx_reo_queue_desc_addr_31_0 951 952 RX_reo_queue_desc_addr_39_32 953 954 955 956 And within the 957 958 Reo_level_mpdu_frame_info: 959 960 Within Rx_mpdu_desc_info_details: 961 962 Mpdu_Sequence_number 963 964 BAR_frame 965 966 Peer_meta_data 967 968 All other fields shall be set to 0 969 970 971 972 <legal all> 973 */ 974 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 975 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 976 #define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 977 978 /* Description REO_ENTRANCE_RING_5_RESERVED_5A 979 980 <legal 0> 981 */ 982 #define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 983 #define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 984 #define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 985 986 /* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON 987 988 Indicates why rxdma pushed the frame to this ring 989 990 991 992 This field is ignored by REO. 993 994 995 996 <enum 0 rxdma_error_detected> RXDMA detected an error an 997 pushed this frame to this queue 998 999 <enum 1 rxdma_routing_instruction> RXDMA pushed the 1000 frame to this queue per received routing instructions. No 1001 error within RXDMA was detected 1002 1003 <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 1004 result the MSDU link descriptor might not have the 1005 last_msdu_in_mpdu_flag set, but instead WBM might just see a 1006 NULL pointer in the MSDU link descriptor. This is to be 1007 considered a normal condition for this scenario. 1008 1009 1010 1011 <legal 0 - 2> 1012 */ 1013 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 1014 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 1015 #define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 1016 1017 /* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE 1018 1019 Field only valid when 'rxdma_push_reason' set to 1020 'rxdma_error_detected'. 1021 1022 1023 1024 This field is ignored by REO. 1025 1026 1027 1028 <enum 0 rxdma_overflow_err>MPDU frame is not complete 1029 due to a FIFO overflow error in RXPCU. 1030 1031 <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 1032 due to receiving incomplete MPDU from the PHY 1033 1034 1035 <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 1036 error or CRYPTO received an encrypted frame, but did not get 1037 a valid corresponding key id in the peer entry. 1038 1039 <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 1040 error 1041 1042 <enum 5 rxdma_unecrypted_err>CRYPTO reported an 1043 unencrypted frame error when encrypted was expected 1044 1045 <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 1046 length error 1047 1048 <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 1049 number of MSDUs allowed in an MPDU got exceeded 1050 1051 <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 1052 error 1053 1054 <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 1055 parsing error 1056 1057 <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 1058 during SA search 1059 1060 <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 1061 during DA search 1062 1063 <enum 12 rxdma_flow_timeout_err>RX OLE reported a 1064 timeout during flow search 1065 1066 <enum 13 Rxdma_flush_request>RXDMA received a flush 1067 request 1068 */ 1069 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 1070 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 1071 #define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c 1072 1073 /* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER 1074 1075 Field only valid when Reo_level_mpdu_frame_info. 1076 1077 Rx_mpdu_desc_info_details. 1078 1079 Fragment_flag is set. 1080 1081 1082 1083 The fragment number from the 802.11 header. 1084 1085 1086 1087 Note that the sequence number is embedded in field: 1088 Reo_level_mpdu_frame_info. 1089 1090 Rx_mpdu_desc_info_details. 1091 1092 Mpdu_Sequence_number 1093 1094 1095 1096 <legal all> 1097 */ 1098 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 1099 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 1100 #define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 1101 1102 /* Description REO_ENTRANCE_RING_6_RESERVED_6A 1103 1104 <legal 0> 1105 */ 1106 #define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 1107 #define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 11 1108 #define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfffff800 1109 1110 /* Description REO_ENTRANCE_RING_7_RESERVED_7A 1111 1112 <legal 0> 1113 */ 1114 #define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c 1115 #define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0 1116 #define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff 1117 1118 /* Description REO_ENTRANCE_RING_7_RING_ID 1119 1120 Consumer: SW/REO/DEBUG 1121 1122 Producer: SRNG (of RXDMA) 1123 1124 1125 1126 For debugging. 1127 1128 This field is filled in by the SRNG module. 1129 1130 It help to identify the ring that is being looked <legal 1131 all> 1132 */ 1133 #define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c 1134 #define REO_ENTRANCE_RING_7_RING_ID_LSB 20 1135 #define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 1136 1137 /* Description REO_ENTRANCE_RING_7_LOOPING_COUNT 1138 1139 Consumer: SW/REO/DEBUG 1140 1141 Producer: SRNG (of RXDMA) 1142 1143 1144 1145 For debugging. 1146 1147 This field is filled in by the SRNG module. 1148 1149 1150 1151 A count value that indicates the number of times the 1152 producer of entries into this Ring has looped around the 1153 ring. 1154 1155 At initialization time, this value is set to 0. On the 1156 first loop, this value is set to 1. After the max value is 1157 reached allowed by the number of bits for this field, the 1158 count value continues with 0 again. 1159 1160 1161 1162 In case SW is the consumer of the ring entries, it can 1163 use this field to figure out up to where the producer of 1164 entries has created new entries. This eliminates the need to 1165 check where the head pointer' of the ring is located once 1166 the SW starts processing an interrupt indicating that new 1167 entries have been put into this ring... 1168 1169 1170 1171 Also note that SW if it wants only needs to look at the 1172 LSB bit of this count value. 1173 1174 <legal all> 1175 */ 1176 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 1177 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 1178 #define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 1179 1180 1181 #endif // _REO_ENTRANCE_RING_H_ 1182