1  /*
2   * Copyright (c) 2016 The Linux Foundation. All rights reserved.
3   *
4   * Permission to use, copy, modify, and/or distribute this software for
5   * any purpose with or without fee is hereby granted, provided that the
6   * above copyright notice and this permission notice appear in all
7   * copies.
8   *
9   * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10   * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11   * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12   * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13   * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14   * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15   * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16   * PERFORMANCE OF THIS SOFTWARE.
17   */
18  
19  // $ATH_LICENSE_HW_HDR_C$
20  //
21  // DO NOT EDIT!  This file is automatically generated
22  //               These definitions are tied to a particular hardware layout
23  
24  
25  #ifndef _RX_ATTENTION_H_
26  #define _RX_ATTENTION_H_
27  #if !defined(__ASSEMBLER__)
28  #endif
29  
30  
31  // ################ START SUMMARY #################
32  //
33  //	Dword	Fields
34  //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
35  //	1	first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31]
36  //	2	flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31]
37  //
38  // ################ END SUMMARY #################
39  
40  #define NUM_OF_DWORDS_RX_ATTENTION 3
41  
42  struct rx_attention {
43               uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
44                        sw_frame_group_id               :  7, //[8:2]
45                        reserved_0                      :  7, //[15:9]
46                        phy_ppdu_id                     : 16; //[31:16]
47               uint32_t first_mpdu                      :  1, //[0]
48                        reserved_1a                     :  1, //[1]
49                        mcast_bcast                     :  1, //[2]
50                        ast_index_not_found             :  1, //[3]
51                        ast_index_timeout               :  1, //[4]
52                        power_mgmt                      :  1, //[5]
53                        non_qos                         :  1, //[6]
54                        null_data                       :  1, //[7]
55                        mgmt_type                       :  1, //[8]
56                        ctrl_type                       :  1, //[9]
57                        more_data                       :  1, //[10]
58                        eosp                            :  1, //[11]
59                        a_msdu_error                    :  1, //[12]
60                        fragment_flag                   :  1, //[13]
61                        order                           :  1, //[14]
62                        cce_match                       :  1, //[15]
63                        overflow_err                    :  1, //[16]
64                        msdu_length_err                 :  1, //[17]
65                        tcp_udp_chksum_fail             :  1, //[18]
66                        ip_chksum_fail                  :  1, //[19]
67                        sa_idx_invalid                  :  1, //[20]
68                        da_idx_invalid                  :  1, //[21]
69                        reserved_1b                     :  1, //[22]
70                        rx_in_tx_decrypt_byp            :  1, //[23]
71                        encrypt_required                :  1, //[24]
72                        directed                        :  1, //[25]
73                        buffer_fragment                 :  1, //[26]
74                        mpdu_length_err                 :  1, //[27]
75                        tkip_mic_err                    :  1, //[28]
76                        decrypt_err                     :  1, //[29]
77                        unencrypted_frame_err           :  1, //[30]
78                        fcs_err                         :  1; //[31]
79               uint32_t flow_idx_timeout                :  1, //[0]
80                        flow_idx_invalid                :  1, //[1]
81                        wifi_parser_error               :  1, //[2]
82                        amsdu_parser_error              :  1, //[3]
83                        sa_idx_timeout                  :  1, //[4]
84                        da_idx_timeout                  :  1, //[5]
85                        msdu_limit_error                :  1, //[6]
86                        da_is_valid                     :  1, //[7]
87                        da_is_mcbc                      :  1, //[8]
88                        sa_is_valid                     :  1, //[9]
89                        decrypt_status_code             :  3, //[12:10]
90                        rx_bitmap_not_updated           :  1, //[13]
91                        reserved_2                      : 17, //[30:14]
92                        msdu_done                       :  1; //[31]
93  };
94  
95  /*
96  
97  rxpcu_mpdu_filter_in_category
98  
99  			Field indicates what the reason was that this MPDU frame
100  			was allowed to come into the receive path by RXPCU
101  
102  			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
103  			frame filter programming of rxpcu
104  
105  			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
106  			regular frame filter and would have been dropped, were it
107  			not for the frame fitting into the 'monitor_client'
108  			category.
109  
110  			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
111  			regular frame filter and also did not pass the
112  			rxpcu_monitor_client filter. It would have been dropped
113  			accept that it did pass the 'monitor_other' category.
114  
115  			<legal 0-2>
116  
117  sw_frame_group_id
118  
119  			SW processes frames based on certain classifications.
120  			This field indicates to what sw classification this MPDU is
121  			mapped.
122  
123  			The classification is given in priority order
124  
125  
126  
127  			<enum 0 sw_frame_group_NDP_frame>
128  
129  
130  
131  			<enum 1 sw_frame_group_Multicast_data>
132  
133  			<enum 2 sw_frame_group_Unicast_data>
134  
135  			<enum 3 sw_frame_group_Null_data > This includes mpdus
136  			of type Data Null as well as QoS Data Null
137  
138  
139  
140  			<enum 4 sw_frame_group_mgmt_0000 >
141  
142  			<enum 5 sw_frame_group_mgmt_0001 >
143  
144  			<enum 6 sw_frame_group_mgmt_0010 >
145  
146  			<enum 7 sw_frame_group_mgmt_0011 >
147  
148  			<enum 8 sw_frame_group_mgmt_0100 >
149  
150  			<enum 9 sw_frame_group_mgmt_0101 >
151  
152  			<enum 10 sw_frame_group_mgmt_0110 >
153  
154  			<enum 11 sw_frame_group_mgmt_0111 >
155  
156  			<enum 12 sw_frame_group_mgmt_1000 >
157  
158  			<enum 13 sw_frame_group_mgmt_1001 >
159  
160  			<enum 14 sw_frame_group_mgmt_1010 >
161  
162  			<enum 15 sw_frame_group_mgmt_1011 >
163  
164  			<enum 16 sw_frame_group_mgmt_1100 >
165  
166  			<enum 17 sw_frame_group_mgmt_1101 >
167  
168  			<enum 18 sw_frame_group_mgmt_1110 >
169  
170  			<enum 19 sw_frame_group_mgmt_1111 >
171  
172  
173  
174  			<enum 20 sw_frame_group_ctrl_0000 >
175  
176  			<enum 21 sw_frame_group_ctrl_0001 >
177  
178  			<enum 22 sw_frame_group_ctrl_0010 >
179  
180  			<enum 23 sw_frame_group_ctrl_0011 >
181  
182  			<enum 24 sw_frame_group_ctrl_0100 >
183  
184  			<enum 25 sw_frame_group_ctrl_0101 >
185  
186  			<enum 26 sw_frame_group_ctrl_0110 >
187  
188  			<enum 27 sw_frame_group_ctrl_0111 >
189  
190  			<enum 28 sw_frame_group_ctrl_1000 >
191  
192  			<enum 29 sw_frame_group_ctrl_1001 >
193  
194  			<enum 30 sw_frame_group_ctrl_1010 >
195  
196  			<enum 31 sw_frame_group_ctrl_1011 >
197  
198  			<enum 32 sw_frame_group_ctrl_1100 >
199  
200  			<enum 33 sw_frame_group_ctrl_1101 >
201  
202  			<enum 34 sw_frame_group_ctrl_1110 >
203  
204  			<enum 35 sw_frame_group_ctrl_1111 >
205  
206  
207  
208  			<enum 36 sw_frame_group_unsupported> This covers type 3
209  			and protocol version != 0
210  
211  
212  
213  
214  
215  
216  			<legal 0-37>
217  
218  reserved_0
219  
220  			<legal 0>
221  
222  phy_ppdu_id
223  
224  			A ppdu counter value that PHY increments for every PPDU
225  			received. The counter value wraps around
226  
227  			<legal all>
228  
229  first_mpdu
230  
231  			Indicates the first MSDU of the PPDU.  If both
232  			first_mpdu and last_mpdu are set in the MSDU then this is a
233  			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
234  			in an A-MPDU shall have both first_mpdu and last_mpdu bits
235  			set to 0.  The PPDU start status will only be valid when
236  			this bit is set.
237  
238  reserved_1a
239  
240  			<legal 0>
241  
242  mcast_bcast
243  
244  			Multicast / broadcast indicator.  Only set when the MAC
245  			address 1 bit 0 is set indicating mcast/bcast and the BSSID
246  			matches one of the 4 BSSID registers. Only set when
247  			first_msdu is set.
248  
249  ast_index_not_found
250  
251  			Only valid when first_msdu is set.
252  
253  
254  
255  			Indicates no AST matching entries within the the max
256  			search count.
257  
258  ast_index_timeout
259  
260  			Only valid when first_msdu is set.
261  
262  
263  
264  			Indicates an unsuccessful search in the address seach
265  			table due to timeout.
266  
267  power_mgmt
268  
269  			Power management bit set in the 802.11 header.  Only set
270  			when first_msdu is set.
271  
272  non_qos
273  
274  			Set if packet is not a non-QoS data frame.  Only set
275  			when first_msdu is set.
276  
277  null_data
278  
279  			Set if frame type indicates either null data or QoS null
280  			data format.  Only set when first_msdu is set.
281  
282  mgmt_type
283  
284  			Set if packet is a management packet.  Only set when
285  			first_msdu is set.
286  
287  ctrl_type
288  
289  			Set if packet is a control packet.  Only set when
290  			first_msdu is set.
291  
292  more_data
293  
294  			Set if more bit in frame control is set.  Only set when
295  			first_msdu is set.
296  
297  eosp
298  
299  			Set if the EOSP (end of service period) bit in the QoS
300  			control field is set.  Only set when first_msdu is set.
301  
302  a_msdu_error
303  
304  			Set if number of MSDUs in A-MSDU is above a threshold or
305  			if the size of the MSDU is invalid.  This receive buffer
306  			will contain all of the remainder of the MSDUs in this MPDU
307  			without decapsulation.
308  
309  fragment_flag
310  
311  			Indicates that this is an 802.11 fragment frame.  This
312  			is set when either the more_frag bit is set in the frame
313  			control or the fragment number is not zero.  Only set when
314  			first_msdu is set.
315  
316  order
317  
318  			Set if the order bit in the frame control is set.  Only
319  			set when first_msdu is set.
320  
321  cce_match
322  
323  			Indicates that this status has a corresponding MSDU that
324  			requires FW processing.  The OLE will have classification
325  			ring mask registers which will indicate the ring(s) for
326  			packets and descriptors which need FW attention.
327  
328  overflow_err
329  
330  			RXPCU Receive FIFO ran out of space to receive the full
331  			MPDU. Therefor this MPDU is terminated early and is thus
332  			corrupted.
333  
334  
335  
336  			This MPDU will not be ACKed.
337  
338  			RXPCU might still be able to correctly receive the
339  			following MPDUs in the PPDU if enough fifo space became
340  			available in time
341  
342  msdu_length_err
343  
344  			Indicates that the MSDU length from the 802.3
345  			encapsulated length field extends beyond the MPDU boundary
346  			or if the length is less than 14 bytes.
347  
348  			Merged with original other_msdu_err: Indicates that the
349  			MSDU threshold was exceeded and thus all the rest of the
350  			MSDUs will not be scattered and will not be decasulated but
351  			will be DMA'ed in RAW format as a single MSDU buffer
352  
353  tcp_udp_chksum_fail
354  
355  			Indicates that the computed checksum (tcp_udp_chksum)
356  			did not match the checksum in the TCP/UDP header.
357  
358  ip_chksum_fail
359  
360  			Indicates that the computed checksum did not match the
361  			checksum in the IP header.
362  
363  sa_idx_invalid
364  
365  			Indicates no matching entry was found in the address
366  			search table for the source MAC address.
367  
368  da_idx_invalid
369  
370  			Indicates no matching entry was found in the address
371  			search table for the destination MAC address.
372  
373  reserved_1b
374  
375  
376  rx_in_tx_decrypt_byp
377  
378  			Indicates that RX packet is not decrypted as Crypto is
379  			busy with TX packet processing.
380  
381  encrypt_required
382  
383  			Indicates that this data type frame is not encrypted
384  			even if the policy for this MPDU requires encryption as
385  			indicated in the peer entry key type.
386  
387  directed
388  
389  			MPDU is a directed packet which means that the RA
390  			matched our STA addresses.  In proxySTA it means that the TA
391  			matched an entry in our address search table with the
392  			corresponding no_ack bit is the address search entry
393  			cleared.
394  
395  buffer_fragment
396  
397  			Indicates that at least one of the rx buffers has been
398  			fragmented.  If set the FW should look at the rx_frag_info
399  			descriptor described below.
400  
401  mpdu_length_err
402  
403  			Indicates that the MPDU was pre-maturely terminated
404  			resulting in a truncated MPDU.  Don't trust the MPDU length
405  			field.
406  
407  tkip_mic_err
408  
409  			Indicates that the MPDU Michael integrity check failed
410  
411  decrypt_err
412  
413  			Indicates that the MPDU decrypt integrity check failed
414  
415  unencrypted_frame_err
416  
417  			Copied here by RX OLE from the RX_MPDU_END TLV
418  
419  fcs_err
420  
421  			Indicates that the MPDU FCS check failed
422  
423  flow_idx_timeout
424  
425  			Indicates an unsuccessful flow search due to the
426  			expiring of the search timer.
427  
428  			<legal all>
429  
430  flow_idx_invalid
431  
432  			flow id is not valid
433  
434  			<legal all>
435  
436  wifi_parser_error
437  
438  			TODO: add details to the description
439  
440  			<legal all>
441  
442  amsdu_parser_error
443  
444  			A-MSDU could not be properly de-agregated.
445  
446  			<legal all>
447  
448  sa_idx_timeout
449  
450  			Indicates an unsuccessful MAC source address search due
451  			to the expiring of the search timer.
452  
453  da_idx_timeout
454  
455  			Indicates an unsuccessful MAC destination address search
456  			due to the expiring of the search timer.
457  
458  msdu_limit_error
459  
460  			Indicates that the MSDU threshold was exceeded and thus
461  			all the rest of the MSDUs will not be scattered and will not
462  			be decasulated but will be DMA'ed in RAW format as a single
463  			MSDU buffer
464  
465  da_is_valid
466  
467  			Indicates that OLE found a valid DA entry
468  
469  da_is_mcbc
470  
471  			Field Only valid if da_is_valid is set
472  
473  
474  
475  			Indicates the DA address was a Multicast of Broadcast
476  			address.
477  
478  sa_is_valid
479  
480  			Indicates that OLE found a valid SA entry
481  
482  decrypt_status_code
483  
484  			Field provides insight into the decryption performed
485  
486  
487  
488  			<enum 0 decrypt_ok> Frame had protection enabled and
489  			decrypted properly
490  
491  			<enum 1 decrypt_unprotected_frame > Frame is unprotected
492  			and hence bypassed
493  
494  			<enum 2 decrypt_data_err > Frame has protection enabled
495  			and could not be properly decrypted due to MIC/ICV mismatch
496  			etc.
497  
498  			<enum 3 decrypt_key_invalid > Frame has protection
499  			enabled but the key that was required to decrypt this frame
500  			was not valid
501  
502  			<enum 4 decrypt_peer_entry_invalid > Frame has
503  			protection enabled but the key that was required to decrypt
504  			this frame was not valid
505  
506  			<enum 5 decrypt_other > Reserved for other indications
507  
508  
509  
510  			<legal 0 - 5>
511  
512  rx_bitmap_not_updated
513  
514  			Frame is received, but RXPCU could not update the
515  			receive bitmap due to (temporary) fifo contraints.
516  
517  			<legal all>
518  
519  reserved_2
520  
521  			<legal 0>
522  
523  msdu_done
524  
525  			If set indicates that the RX packet data, RX header
526  			data, RX PPDU start descriptor, RX MPDU start/end
527  			descriptor, RX MSDU start/end descriptors and RX Attention
528  			descriptor are all valid.  This bit must be in the last
529  			octet of the descriptor.
530  */
531  
532  
533  /* Description		RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY
534  
535  			Field indicates what the reason was that this MPDU frame
536  			was allowed to come into the receive path by RXPCU
537  
538  			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
539  			frame filter programming of rxpcu
540  
541  			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
542  			regular frame filter and would have been dropped, were it
543  			not for the frame fitting into the 'monitor_client'
544  			category.
545  
546  			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
547  			regular frame filter and also did not pass the
548  			rxpcu_monitor_client filter. It would have been dropped
549  			accept that it did pass the 'monitor_other' category.
550  
551  			<legal 0-2>
552  */
553  #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
554  #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
555  #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
556  
557  /* Description		RX_ATTENTION_0_SW_FRAME_GROUP_ID
558  
559  			SW processes frames based on certain classifications.
560  			This field indicates to what sw classification this MPDU is
561  			mapped.
562  
563  			The classification is given in priority order
564  
565  
566  
567  			<enum 0 sw_frame_group_NDP_frame>
568  
569  
570  
571  			<enum 1 sw_frame_group_Multicast_data>
572  
573  			<enum 2 sw_frame_group_Unicast_data>
574  
575  			<enum 3 sw_frame_group_Null_data > This includes mpdus
576  			of type Data Null as well as QoS Data Null
577  
578  
579  
580  			<enum 4 sw_frame_group_mgmt_0000 >
581  
582  			<enum 5 sw_frame_group_mgmt_0001 >
583  
584  			<enum 6 sw_frame_group_mgmt_0010 >
585  
586  			<enum 7 sw_frame_group_mgmt_0011 >
587  
588  			<enum 8 sw_frame_group_mgmt_0100 >
589  
590  			<enum 9 sw_frame_group_mgmt_0101 >
591  
592  			<enum 10 sw_frame_group_mgmt_0110 >
593  
594  			<enum 11 sw_frame_group_mgmt_0111 >
595  
596  			<enum 12 sw_frame_group_mgmt_1000 >
597  
598  			<enum 13 sw_frame_group_mgmt_1001 >
599  
600  			<enum 14 sw_frame_group_mgmt_1010 >
601  
602  			<enum 15 sw_frame_group_mgmt_1011 >
603  
604  			<enum 16 sw_frame_group_mgmt_1100 >
605  
606  			<enum 17 sw_frame_group_mgmt_1101 >
607  
608  			<enum 18 sw_frame_group_mgmt_1110 >
609  
610  			<enum 19 sw_frame_group_mgmt_1111 >
611  
612  
613  
614  			<enum 20 sw_frame_group_ctrl_0000 >
615  
616  			<enum 21 sw_frame_group_ctrl_0001 >
617  
618  			<enum 22 sw_frame_group_ctrl_0010 >
619  
620  			<enum 23 sw_frame_group_ctrl_0011 >
621  
622  			<enum 24 sw_frame_group_ctrl_0100 >
623  
624  			<enum 25 sw_frame_group_ctrl_0101 >
625  
626  			<enum 26 sw_frame_group_ctrl_0110 >
627  
628  			<enum 27 sw_frame_group_ctrl_0111 >
629  
630  			<enum 28 sw_frame_group_ctrl_1000 >
631  
632  			<enum 29 sw_frame_group_ctrl_1001 >
633  
634  			<enum 30 sw_frame_group_ctrl_1010 >
635  
636  			<enum 31 sw_frame_group_ctrl_1011 >
637  
638  			<enum 32 sw_frame_group_ctrl_1100 >
639  
640  			<enum 33 sw_frame_group_ctrl_1101 >
641  
642  			<enum 34 sw_frame_group_ctrl_1110 >
643  
644  			<enum 35 sw_frame_group_ctrl_1111 >
645  
646  
647  
648  			<enum 36 sw_frame_group_unsupported> This covers type 3
649  			and protocol version != 0
650  
651  
652  
653  
654  
655  
656  			<legal 0-37>
657  */
658  #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
659  #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB                         2
660  #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
661  
662  /* Description		RX_ATTENTION_0_RESERVED_0
663  
664  			<legal 0>
665  */
666  #define RX_ATTENTION_0_RESERVED_0_OFFSET                             0x00000000
667  #define RX_ATTENTION_0_RESERVED_0_LSB                                9
668  #define RX_ATTENTION_0_RESERVED_0_MASK                               0x0000fe00
669  
670  /* Description		RX_ATTENTION_0_PHY_PPDU_ID
671  
672  			A ppdu counter value that PHY increments for every PPDU
673  			received. The counter value wraps around
674  
675  			<legal all>
676  */
677  #define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET                            0x00000000
678  #define RX_ATTENTION_0_PHY_PPDU_ID_LSB                               16
679  #define RX_ATTENTION_0_PHY_PPDU_ID_MASK                              0xffff0000
680  
681  /* Description		RX_ATTENTION_1_FIRST_MPDU
682  
683  			Indicates the first MSDU of the PPDU.  If both
684  			first_mpdu and last_mpdu are set in the MSDU then this is a
685  			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
686  			in an A-MPDU shall have both first_mpdu and last_mpdu bits
687  			set to 0.  The PPDU start status will only be valid when
688  			this bit is set.
689  */
690  #define RX_ATTENTION_1_FIRST_MPDU_OFFSET                             0x00000004
691  #define RX_ATTENTION_1_FIRST_MPDU_LSB                                0
692  #define RX_ATTENTION_1_FIRST_MPDU_MASK                               0x00000001
693  
694  /* Description		RX_ATTENTION_1_RESERVED_1A
695  
696  			<legal 0>
697  */
698  #define RX_ATTENTION_1_RESERVED_1A_OFFSET                            0x00000004
699  #define RX_ATTENTION_1_RESERVED_1A_LSB                               1
700  #define RX_ATTENTION_1_RESERVED_1A_MASK                              0x00000002
701  
702  /* Description		RX_ATTENTION_1_MCAST_BCAST
703  
704  			Multicast / broadcast indicator.  Only set when the MAC
705  			address 1 bit 0 is set indicating mcast/bcast and the BSSID
706  			matches one of the 4 BSSID registers. Only set when
707  			first_msdu is set.
708  */
709  #define RX_ATTENTION_1_MCAST_BCAST_OFFSET                            0x00000004
710  #define RX_ATTENTION_1_MCAST_BCAST_LSB                               2
711  #define RX_ATTENTION_1_MCAST_BCAST_MASK                              0x00000004
712  
713  /* Description		RX_ATTENTION_1_AST_INDEX_NOT_FOUND
714  
715  			Only valid when first_msdu is set.
716  
717  
718  
719  			Indicates no AST matching entries within the the max
720  			search count.
721  */
722  #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET                    0x00000004
723  #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB                       3
724  #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK                      0x00000008
725  
726  /* Description		RX_ATTENTION_1_AST_INDEX_TIMEOUT
727  
728  			Only valid when first_msdu is set.
729  
730  
731  
732  			Indicates an unsuccessful search in the address seach
733  			table due to timeout.
734  */
735  #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET                      0x00000004
736  #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB                         4
737  #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK                        0x00000010
738  
739  /* Description		RX_ATTENTION_1_POWER_MGMT
740  
741  			Power management bit set in the 802.11 header.  Only set
742  			when first_msdu is set.
743  */
744  #define RX_ATTENTION_1_POWER_MGMT_OFFSET                             0x00000004
745  #define RX_ATTENTION_1_POWER_MGMT_LSB                                5
746  #define RX_ATTENTION_1_POWER_MGMT_MASK                               0x00000020
747  
748  /* Description		RX_ATTENTION_1_NON_QOS
749  
750  			Set if packet is not a non-QoS data frame.  Only set
751  			when first_msdu is set.
752  */
753  #define RX_ATTENTION_1_NON_QOS_OFFSET                                0x00000004
754  #define RX_ATTENTION_1_NON_QOS_LSB                                   6
755  #define RX_ATTENTION_1_NON_QOS_MASK                                  0x00000040
756  
757  /* Description		RX_ATTENTION_1_NULL_DATA
758  
759  			Set if frame type indicates either null data or QoS null
760  			data format.  Only set when first_msdu is set.
761  */
762  #define RX_ATTENTION_1_NULL_DATA_OFFSET                              0x00000004
763  #define RX_ATTENTION_1_NULL_DATA_LSB                                 7
764  #define RX_ATTENTION_1_NULL_DATA_MASK                                0x00000080
765  
766  /* Description		RX_ATTENTION_1_MGMT_TYPE
767  
768  			Set if packet is a management packet.  Only set when
769  			first_msdu is set.
770  */
771  #define RX_ATTENTION_1_MGMT_TYPE_OFFSET                              0x00000004
772  #define RX_ATTENTION_1_MGMT_TYPE_LSB                                 8
773  #define RX_ATTENTION_1_MGMT_TYPE_MASK                                0x00000100
774  
775  /* Description		RX_ATTENTION_1_CTRL_TYPE
776  
777  			Set if packet is a control packet.  Only set when
778  			first_msdu is set.
779  */
780  #define RX_ATTENTION_1_CTRL_TYPE_OFFSET                              0x00000004
781  #define RX_ATTENTION_1_CTRL_TYPE_LSB                                 9
782  #define RX_ATTENTION_1_CTRL_TYPE_MASK                                0x00000200
783  
784  /* Description		RX_ATTENTION_1_MORE_DATA
785  
786  			Set if more bit in frame control is set.  Only set when
787  			first_msdu is set.
788  */
789  #define RX_ATTENTION_1_MORE_DATA_OFFSET                              0x00000004
790  #define RX_ATTENTION_1_MORE_DATA_LSB                                 10
791  #define RX_ATTENTION_1_MORE_DATA_MASK                                0x00000400
792  
793  /* Description		RX_ATTENTION_1_EOSP
794  
795  			Set if the EOSP (end of service period) bit in the QoS
796  			control field is set.  Only set when first_msdu is set.
797  */
798  #define RX_ATTENTION_1_EOSP_OFFSET                                   0x00000004
799  #define RX_ATTENTION_1_EOSP_LSB                                      11
800  #define RX_ATTENTION_1_EOSP_MASK                                     0x00000800
801  
802  /* Description		RX_ATTENTION_1_A_MSDU_ERROR
803  
804  			Set if number of MSDUs in A-MSDU is above a threshold or
805  			if the size of the MSDU is invalid.  This receive buffer
806  			will contain all of the remainder of the MSDUs in this MPDU
807  			without decapsulation.
808  */
809  #define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET                           0x00000004
810  #define RX_ATTENTION_1_A_MSDU_ERROR_LSB                              12
811  #define RX_ATTENTION_1_A_MSDU_ERROR_MASK                             0x00001000
812  
813  /* Description		RX_ATTENTION_1_FRAGMENT_FLAG
814  
815  			Indicates that this is an 802.11 fragment frame.  This
816  			is set when either the more_frag bit is set in the frame
817  			control or the fragment number is not zero.  Only set when
818  			first_msdu is set.
819  */
820  #define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET                          0x00000004
821  #define RX_ATTENTION_1_FRAGMENT_FLAG_LSB                             13
822  #define RX_ATTENTION_1_FRAGMENT_FLAG_MASK                            0x00002000
823  
824  /* Description		RX_ATTENTION_1_ORDER
825  
826  			Set if the order bit in the frame control is set.  Only
827  			set when first_msdu is set.
828  */
829  #define RX_ATTENTION_1_ORDER_OFFSET                                  0x00000004
830  #define RX_ATTENTION_1_ORDER_LSB                                     14
831  #define RX_ATTENTION_1_ORDER_MASK                                    0x00004000
832  
833  /* Description		RX_ATTENTION_1_CCE_MATCH
834  
835  			Indicates that this status has a corresponding MSDU that
836  			requires FW processing.  The OLE will have classification
837  			ring mask registers which will indicate the ring(s) for
838  			packets and descriptors which need FW attention.
839  */
840  #define RX_ATTENTION_1_CCE_MATCH_OFFSET                              0x00000004
841  #define RX_ATTENTION_1_CCE_MATCH_LSB                                 15
842  #define RX_ATTENTION_1_CCE_MATCH_MASK                                0x00008000
843  
844  /* Description		RX_ATTENTION_1_OVERFLOW_ERR
845  
846  			RXPCU Receive FIFO ran out of space to receive the full
847  			MPDU. Therefor this MPDU is terminated early and is thus
848  			corrupted.
849  
850  
851  
852  			This MPDU will not be ACKed.
853  
854  			RXPCU might still be able to correctly receive the
855  			following MPDUs in the PPDU if enough fifo space became
856  			available in time
857  */
858  #define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET                           0x00000004
859  #define RX_ATTENTION_1_OVERFLOW_ERR_LSB                              16
860  #define RX_ATTENTION_1_OVERFLOW_ERR_MASK                             0x00010000
861  
862  /* Description		RX_ATTENTION_1_MSDU_LENGTH_ERR
863  
864  			Indicates that the MSDU length from the 802.3
865  			encapsulated length field extends beyond the MPDU boundary
866  			or if the length is less than 14 bytes.
867  
868  			Merged with original other_msdu_err: Indicates that the
869  			MSDU threshold was exceeded and thus all the rest of the
870  			MSDUs will not be scattered and will not be decasulated but
871  			will be DMA'ed in RAW format as a single MSDU buffer
872  */
873  #define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET                        0x00000004
874  #define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB                           17
875  #define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK                          0x00020000
876  
877  /* Description		RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL
878  
879  			Indicates that the computed checksum (tcp_udp_chksum)
880  			did not match the checksum in the TCP/UDP header.
881  */
882  #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000004
883  #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB                       18
884  #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK                      0x00040000
885  
886  /* Description		RX_ATTENTION_1_IP_CHKSUM_FAIL
887  
888  			Indicates that the computed checksum did not match the
889  			checksum in the IP header.
890  */
891  #define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET                         0x00000004
892  #define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB                            19
893  #define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK                           0x00080000
894  
895  /* Description		RX_ATTENTION_1_SA_IDX_INVALID
896  
897  			Indicates no matching entry was found in the address
898  			search table for the source MAC address.
899  */
900  #define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET                         0x00000004
901  #define RX_ATTENTION_1_SA_IDX_INVALID_LSB                            20
902  #define RX_ATTENTION_1_SA_IDX_INVALID_MASK                           0x00100000
903  
904  /* Description		RX_ATTENTION_1_DA_IDX_INVALID
905  
906  			Indicates no matching entry was found in the address
907  			search table for the destination MAC address.
908  */
909  #define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET                         0x00000004
910  #define RX_ATTENTION_1_DA_IDX_INVALID_LSB                            21
911  #define RX_ATTENTION_1_DA_IDX_INVALID_MASK                           0x00200000
912  
913  /* Description		RX_ATTENTION_1_RESERVED_1B
914  
915  */
916  #define RX_ATTENTION_1_RESERVED_1B_OFFSET                            0x00000004
917  #define RX_ATTENTION_1_RESERVED_1B_LSB                               22
918  #define RX_ATTENTION_1_RESERVED_1B_MASK                              0x00400000
919  
920  /* Description		RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP
921  
922  			Indicates that RX packet is not decrypted as Crypto is
923  			busy with TX packet processing.
924  */
925  #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET                   0x00000004
926  #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB                      23
927  #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK                     0x00800000
928  
929  /* Description		RX_ATTENTION_1_ENCRYPT_REQUIRED
930  
931  			Indicates that this data type frame is not encrypted
932  			even if the policy for this MPDU requires encryption as
933  			indicated in the peer entry key type.
934  */
935  #define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET                       0x00000004
936  #define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB                          24
937  #define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK                         0x01000000
938  
939  /* Description		RX_ATTENTION_1_DIRECTED
940  
941  			MPDU is a directed packet which means that the RA
942  			matched our STA addresses.  In proxySTA it means that the TA
943  			matched an entry in our address search table with the
944  			corresponding no_ack bit is the address search entry
945  			cleared.
946  */
947  #define RX_ATTENTION_1_DIRECTED_OFFSET                               0x00000004
948  #define RX_ATTENTION_1_DIRECTED_LSB                                  25
949  #define RX_ATTENTION_1_DIRECTED_MASK                                 0x02000000
950  
951  /* Description		RX_ATTENTION_1_BUFFER_FRAGMENT
952  
953  			Indicates that at least one of the rx buffers has been
954  			fragmented.  If set the FW should look at the rx_frag_info
955  			descriptor described below.
956  */
957  #define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET                        0x00000004
958  #define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB                           26
959  #define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK                          0x04000000
960  
961  /* Description		RX_ATTENTION_1_MPDU_LENGTH_ERR
962  
963  			Indicates that the MPDU was pre-maturely terminated
964  			resulting in a truncated MPDU.  Don't trust the MPDU length
965  			field.
966  */
967  #define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET                        0x00000004
968  #define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB                           27
969  #define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK                          0x08000000
970  
971  /* Description		RX_ATTENTION_1_TKIP_MIC_ERR
972  
973  			Indicates that the MPDU Michael integrity check failed
974  */
975  #define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET                           0x00000004
976  #define RX_ATTENTION_1_TKIP_MIC_ERR_LSB                              28
977  #define RX_ATTENTION_1_TKIP_MIC_ERR_MASK                             0x10000000
978  
979  /* Description		RX_ATTENTION_1_DECRYPT_ERR
980  
981  			Indicates that the MPDU decrypt integrity check failed
982  */
983  #define RX_ATTENTION_1_DECRYPT_ERR_OFFSET                            0x00000004
984  #define RX_ATTENTION_1_DECRYPT_ERR_LSB                               29
985  #define RX_ATTENTION_1_DECRYPT_ERR_MASK                              0x20000000
986  
987  /* Description		RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR
988  
989  			Copied here by RX OLE from the RX_MPDU_END TLV
990  */
991  #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET                  0x00000004
992  #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB                     30
993  #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK                    0x40000000
994  
995  /* Description		RX_ATTENTION_1_FCS_ERR
996  
997  			Indicates that the MPDU FCS check failed
998  */
999  #define RX_ATTENTION_1_FCS_ERR_OFFSET                                0x00000004
1000  #define RX_ATTENTION_1_FCS_ERR_LSB                                   31
1001  #define RX_ATTENTION_1_FCS_ERR_MASK                                  0x80000000
1002  
1003  /* Description		RX_ATTENTION_2_FLOW_IDX_TIMEOUT
1004  
1005  			Indicates an unsuccessful flow search due to the
1006  			expiring of the search timer.
1007  
1008  			<legal all>
1009  */
1010  #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET                       0x00000008
1011  #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB                          0
1012  #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK                         0x00000001
1013  
1014  /* Description		RX_ATTENTION_2_FLOW_IDX_INVALID
1015  
1016  			flow id is not valid
1017  
1018  			<legal all>
1019  */
1020  #define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET                       0x00000008
1021  #define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB                          1
1022  #define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK                         0x00000002
1023  
1024  /* Description		RX_ATTENTION_2_WIFI_PARSER_ERROR
1025  
1026  			TODO: add details to the description
1027  
1028  			<legal all>
1029  */
1030  #define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET                      0x00000008
1031  #define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB                         2
1032  #define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK                        0x00000004
1033  
1034  /* Description		RX_ATTENTION_2_AMSDU_PARSER_ERROR
1035  
1036  			A-MSDU could not be properly de-agregated.
1037  
1038  			<legal all>
1039  */
1040  #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET                     0x00000008
1041  #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB                        3
1042  #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK                       0x00000008
1043  
1044  /* Description		RX_ATTENTION_2_SA_IDX_TIMEOUT
1045  
1046  			Indicates an unsuccessful MAC source address search due
1047  			to the expiring of the search timer.
1048  */
1049  #define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET                         0x00000008
1050  #define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB                            4
1051  #define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK                           0x00000010
1052  
1053  /* Description		RX_ATTENTION_2_DA_IDX_TIMEOUT
1054  
1055  			Indicates an unsuccessful MAC destination address search
1056  			due to the expiring of the search timer.
1057  */
1058  #define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET                         0x00000008
1059  #define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB                            5
1060  #define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK                           0x00000020
1061  
1062  /* Description		RX_ATTENTION_2_MSDU_LIMIT_ERROR
1063  
1064  			Indicates that the MSDU threshold was exceeded and thus
1065  			all the rest of the MSDUs will not be scattered and will not
1066  			be decasulated but will be DMA'ed in RAW format as a single
1067  			MSDU buffer
1068  */
1069  #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET                       0x00000008
1070  #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB                          6
1071  #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK                         0x00000040
1072  
1073  /* Description		RX_ATTENTION_2_DA_IS_VALID
1074  
1075  			Indicates that OLE found a valid DA entry
1076  */
1077  #define RX_ATTENTION_2_DA_IS_VALID_OFFSET                            0x00000008
1078  #define RX_ATTENTION_2_DA_IS_VALID_LSB                               7
1079  #define RX_ATTENTION_2_DA_IS_VALID_MASK                              0x00000080
1080  
1081  /* Description		RX_ATTENTION_2_DA_IS_MCBC
1082  
1083  			Field Only valid if da_is_valid is set
1084  
1085  
1086  
1087  			Indicates the DA address was a Multicast of Broadcast
1088  			address.
1089  */
1090  #define RX_ATTENTION_2_DA_IS_MCBC_OFFSET                             0x00000008
1091  #define RX_ATTENTION_2_DA_IS_MCBC_LSB                                8
1092  #define RX_ATTENTION_2_DA_IS_MCBC_MASK                               0x00000100
1093  
1094  /* Description		RX_ATTENTION_2_SA_IS_VALID
1095  
1096  			Indicates that OLE found a valid SA entry
1097  */
1098  #define RX_ATTENTION_2_SA_IS_VALID_OFFSET                            0x00000008
1099  #define RX_ATTENTION_2_SA_IS_VALID_LSB                               9
1100  #define RX_ATTENTION_2_SA_IS_VALID_MASK                              0x00000200
1101  
1102  /* Description		RX_ATTENTION_2_DECRYPT_STATUS_CODE
1103  
1104  			Field provides insight into the decryption performed
1105  
1106  
1107  
1108  			<enum 0 decrypt_ok> Frame had protection enabled and
1109  			decrypted properly
1110  
1111  			<enum 1 decrypt_unprotected_frame > Frame is unprotected
1112  			and hence bypassed
1113  
1114  			<enum 2 decrypt_data_err > Frame has protection enabled
1115  			and could not be properly decrypted due to MIC/ICV mismatch
1116  			etc.
1117  
1118  			<enum 3 decrypt_key_invalid > Frame has protection
1119  			enabled but the key that was required to decrypt this frame
1120  			was not valid
1121  
1122  			<enum 4 decrypt_peer_entry_invalid > Frame has
1123  			protection enabled but the key that was required to decrypt
1124  			this frame was not valid
1125  
1126  			<enum 5 decrypt_other > Reserved for other indications
1127  
1128  
1129  
1130  			<legal 0 - 5>
1131  */
1132  #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET                    0x00000008
1133  #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB                       10
1134  #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK                      0x00001c00
1135  
1136  /* Description		RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED
1137  
1138  			Frame is received, but RXPCU could not update the
1139  			receive bitmap due to (temporary) fifo contraints.
1140  
1141  			<legal all>
1142  */
1143  #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET                  0x00000008
1144  #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB                     13
1145  #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK                    0x00002000
1146  
1147  /* Description		RX_ATTENTION_2_RESERVED_2
1148  
1149  			<legal 0>
1150  */
1151  #define RX_ATTENTION_2_RESERVED_2_OFFSET                             0x00000008
1152  #define RX_ATTENTION_2_RESERVED_2_LSB                                14
1153  #define RX_ATTENTION_2_RESERVED_2_MASK                               0x7fffc000
1154  
1155  /* Description		RX_ATTENTION_2_MSDU_DONE
1156  
1157  			If set indicates that the RX packet data, RX header
1158  			data, RX PPDU start descriptor, RX MPDU start/end
1159  			descriptor, RX MSDU start/end descriptors and RX Attention
1160  			descriptor are all valid.  This bit must be in the last
1161  			octet of the descriptor.
1162  */
1163  #define RX_ATTENTION_2_MSDU_DONE_OFFSET                              0x00000008
1164  #define RX_ATTENTION_2_MSDU_DONE_LSB                                 31
1165  #define RX_ATTENTION_2_MSDU_DONE_MASK                                0x80000000
1166  
1167  
1168  #endif // _RX_ATTENTION_H_
1169